FinFET Replacement Gate Uniformity via Planarization Extraction
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Solution Overview
Problem
Traditional FinFET device fabrication techniques face challenges with topography control and uniformity in gate length due to uneven sacrificial gate material deposition and planarization processes, particularly in scaled FinFET technologies, leading to variations in gate thickness and flaring issues.
Innovation Solution
A method involving forming a fin with a substantially planar insulating layer, depositing sacrificial gate material with uniform thickness, and forming a gate cap material, followed by etching to define a patterned sacrificial gate structure, removing it to create a replacement gate cavity, and forming a replacement gate structure around the fin surfaces, which improves control over gate length and uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional sacrificial gate material deposition and planarization processes are used, then gate structure formation is achieved, but topography control deteriorates and gate length uniformity varies
Solution Approach 1:
The patent removes the planarization step from the traditional process flow by extracting it entirely. Instead of depositing sacrificial gate material and then planarizing, the method deposits the material and directly etches it, eliminating the source of topography control issues and gate length variations
Solution Approach 2:
The patent inverts the traditional sequence by etching the sacrificial gate material before removing it, rather than planarizing first. This reversal allows the etch process to define the gate length precisely while the sacrificial material is still in place, avoiding the flaring issues that occur with traditional planarization approaches
2Ease of manufacture
If sacrificial gate material is deposited to fill trenches, then gate structure is formed, but topography control worsens due to uneven deposition
Solution Approach 1:
The patent applies a preliminary planarization layer (e.g., spin-on-glass) before depositing the sacrificial gate material. This preliminary action creates a flat surface that ensures uniform thickness of the sacrificial material during deposition, solving the topography control issue while maintaining ease of manufacture
Solution Approach 2:
The patent introduces an intermediary planarization layer between the trench structure and the sacrificial gate material. This intermediary layer acts as a mediator that absorbs the topography variations, allowing uniform material deposition without requiring complex process control
3Shape
If planarization processes are performed on sacrificial gate material, then surface flatness is achieved, but gate length flaring occurs
Solution Approach 1:
The patent extracts the planarization step entirely from the process flow, replacing it with a direct etch approach. This eliminates the mechanism that causes gate length flaring while still achieving the necessary surface preparation through the preliminary planarization layer
Solution Approach 2:
The patent replaces the mechanical planarization process (CMP) with a chemical etch process. This substitution avoids the mechanical forces and pressure variations that cause flaring, using instead a controlled chemical reaction to define the gate structure with precise dimensional control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances topography control and achieves more uniform gate lengths, reducing operational issues such as slower device performance and variability, by precisely controlling the sacrificial gate material thickness and eliminating the need for planarization processes.
Implementation Method 1
the sacrificial gate material is deposited with a uniform thickness, e.g., by performing a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process
Implementation Method 2
the sacrificial gate material is deposited with a uniform thickness, e.g., by performing a physical vapor deposition (PVD) process or a chemical vapor deposition (CVD) process
Implementation Method 3
performing at least one etching process to define a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material
Data Source
AI summary
One illustrative method disclosed herein includes, among other things, forming at least one layer of insulating material with a substantially planar upper surface that is positioned above the upper surface of the fin, forming a layer of sacrificial gate material on the layer of insulating material, the layer of sacrificial gate material having an as-deposited upper surface and a substantially uniform thickness, forming a layer of gate cap material on the as-deposited upper surface of the layer of sacrificial gate material, forming a patterned sacrificial gate structure comprised of at least the gate cap material and the sacrificial gate material, forming a sidewall spacer adjacent the patterned sacrificial gate structure, removing the patterned sacrificial gate structure and replacing it with a replacement gate structure.