FinFET Resistor Fabrication via Sidewall Silicidation
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Solution Overview
Problem
Existing integrated circuit fabrication techniques face challenges in accurately setting resistance values for passive devices like resistors while minimizing their footprint, especially when integrated with active devices such as FinFETs, as current methods lack precision and efficiency in achieving desired resistance values with minimal space requirements.
Innovation Solution
The method involves forming resistive silicide fin structures on a semiconductor substrate by siliciding the sidewalls of semiconductor fin structures, removing the unsilicided central portions, and connecting the silicide fins to create resistors, allowing for precise resistance value adjustment through the choice of silicide material, fin length, and number of connected fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional resistor fabrication methods are used, then resistance values can be set, but the footprint and space requirements are large
Solution Approach 1:
The patent transitions from planar resistor structures to three-dimensional FinFET-based resistor structures. By utilizing the vertical dimension and sidewall surfaces of the fins, the resistor achieves higher resistance density in a smaller footprint. The silicided sidewalls of multiple fins are connected to form the resistive element, effectively using vertical space to reduce horizontal area requirements.
Solution Approach 2:
The patent applies selective silicidation to specific regions of the FinFET structure. The sidewalls of the fins are silicided to create high-resistance regions, while other portions of the structure maintain their original properties. This localized modification allows precise control of resistance values by adjusting silicide thickness, composition, and formation conditions on specific surfaces.
2Adaptability or versatility
If polysilicon or metal resistors are used, then different resistivity values can be achieved, but the fabrication complexity increases
Solution Approach 1:
The patent uses the same FinFET structure and silicidation process that is already employed for active device fabrication to also create resistors. The silicided sidewalls serve dual purposes: forming the resistive element for passive devices while maintaining compatibility with the active FinFET manufacturing flow. This eliminates the need for separate resistor fabrication processes and materials.
Solution Approach 2:
The patent achieves different resistance values by modifying process parameters rather than changing materials. Resistance is controlled by adjusting silicide thickness, silicide composition (e.g., nickel silicide, cobalt silicide), annealing conditions, and the number/geometry of fins. This parameter-based control simplifies fabrication by using a single material system with tunable properties.
3Area of stationary object
If resistor footprint is minimized, then space is saved, but resistance value tuning precision is reduced
Solution Approach 1:
The resistor is divided into multiple discrete fin structures whose sidewalls are silicided. Each fin contributes to the total resistance, and the overall resistance value is controlled by the number of fins, their dimensions, and the silicide properties. This segmentation allows fine-tuning of resistance by adjusting individual fin parameters or the number of fins in parallel, achieving precision while maintaining small footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of resistors with tight FinFET dimensions, allowing for accurate resistance value establishment and minimal space usage, enhancing the precision and efficiency of resistor fabrication in integrated circuits.
Implementation Method 1
performing an anneal to react the metal of the metal layer with underlying semiconductor material so as to convert semiconductor material on the sidewalls of the semiconductor fin structures to a silicide having a predetermined value of resistance
Implementation Method 2
react the metal of the metal layer with underlying semiconductor material so as to convert semiconductor material on the sidewalls of the semiconductor fin structures to a silicide
Data Source
AI summary
A method includes providing a semiconductor substrate having a plurality of linear semiconductor fin structures spaced apart from one another on a surface of the substrate; siliciding sidewalls of the semiconductor fin structures; removing an unsilicided central portion of each semiconductor fin structure leaving, for a given one of the semiconductor fin structures, a pair of silicide fin structures that are parallel to one another and spaced apart from one another by a distance about equal to a width of the removed unsilicided central portion of the semiconductor fin structure; and forming contacts to conductively connect together a plurality of the silicide fin structures to form a resistor. A resistance value of the resistor is related at least to a type of silicide, a number of contacted adjacent silicide fin structures and a length between two contacts.