FinFET ROM Cell Leakage Control via Vertical Gate Wrapping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor process nodes are scaled down for high-density ROM integrated circuits, maintaining low leakage current and high-speed performance becomes challenging, necessitating new techniques beyond conventional planar transistors.
Innovation Solution
The use of FinFETs with a three-dimensional channel region and a gate structure that wraps around the active region, providing improved control over leakage current and allowing for increased gate width without increased silicon area, combined with isolation transistors to prevent active current flow between adjacent ROM cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar transistors are used in scaled-down semiconductor nodes, then manufacturing simplicity is maintained, but leakage current increases and performance deteriorates
Solution Approach 1:
The patent transitions from planar two-dimensional transistor structures to three-dimensional FinFET structures with channels protruding vertically from the substrate. This dimensional change enables the gate to wrap around and control the channel from multiple sides, dramatically improving leakage current control at scaled-down nodes while maintaining manufacturing feasibility through established FinFET fabrication processes
2Speed
If gate width is increased to improve performance, then speed increases, but silicon area increases
Solution Approach 1:
The FinFET structure utilizes the vertical dimension by creating channels that protrude upward from the substrate surface. This allows the gate width to be effectively increased through the vertical height of the fin structure without consuming additional horizontal silicon area, thereby improving ROM operation speed while maintaining high density
3Quantity of substance
If semiconductor process node is scaled down to increase density, then high density is achieved, but leakage current control becomes difficult
Solution Approach 1:
At scaled-down process nodes, the FinFET structure compensates for reduced dimensional control by utilizing the vertical fin height. The gate wraps around the channel from three sides, providing enhanced electrostatic control that maintains low leakage current even as the device footprint shrinks to achieve high density
Solution Approach 2:
The patent introduces isolation transistors with specific gate configurations that remain in a non-conducting state to electrically isolate adjacent ROM cells. This local quality control prevents active current flow between cells while maintaining the overall high-density layout, addressing leakage issues at the cell level without sacrificing density
Data Source
AI summary
A ROM cell comprises a first first-level contact formed on a first active region of a transistor of a memory cell, a first second-level contact formed on the first first-level contact, wherein the first second-level contact shifts in a first direction with reference to the first first-level contact. The ROM cell further comprises a second first-level contact formed on a second active region of the transistor of the memory cell, wherein the second first-level contact is aligned with the first first-level contact and a second second-level formed on the second first-level contact, wherein the second second-level contact shifts in a second direction with reference to the second first-level contact, and wherein the first direction is opposite to the second direction.