FinFET Routing Layer Segmentation for ESD Protection
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Solution Overview
Problem
FinFET devices face challenges in electrostatic discharge (ESD) protection due to reduced photons reaching the active area and quantum efficiency, caused by conductive lines blocking the active area and insufficient junction size, leading to reduced junction leakage current and performance issues.
Innovation Solution
The semiconductor structure and fabrication method involve forming a semiconductor device with a fin structure where at least a portion of the active region is free from the coverage of the conductive routing layer, allowing more photons to reach the active area and increasing the junction leakage current, thereby enhancing ESD protection and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive routing layer is placed over the fin structure to provide electrical connection, then electrical connectivity is improved, but the active area exposed to photons is reduced
Solution Approach 1:
The conductive routing layer is segmented into discrete portions rather than forming a continuous layer. Gaps are intentionally created in the routing layer to allow photons to reach the active area while maintaining electrical connectivity through the exposed regions. This segmentation resolves the contradiction by allowing both electrical connection and photon access to coexist.
Solution Approach 2:
Different regions of the device are given different properties: areas requiring electrical connectivity have conductive routing layer, while areas requiring photon access have exposed active area. The routing layer is locally modified to provide connectivity where needed while leaving gaps where photon interaction is required, creating spatially varying quality to satisfy both requirements.
2Reliability
If junction size is increased to improve ESD protection, then ESD resistance is improved, but device area is increased
Solution Approach 1:
The fin structure utilizes the vertical dimension to increase junction area without increasing the planar device footprint. By extending the fin height, the junction area is increased in the vertical dimension, providing improved ESD protection while maintaining a compact planar area. This dimensional transition resolves the contradiction between ESD protection and device area.
Solution Approach 2:
The device employs composite material structures including doped semiconductor regions with different conductivity types (n-type and p-type) forming the junction. The fin structure itself is a composite of semiconductor material with controlled doping profiles, creating a multi-layered material system that provides enhanced ESD protection within a compact area through optimized material composition and structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the efficiency of ESD protection by increasing the active area exposed to incident photons, enhancing the semiconductor device's ability to alleviate electrostatic discharge and reduce defects, such as via-induced metal island corrosion and metal electro-migration.
Implementation Method 1
allowing more photons to reach the active area and increasing the junction leakage current
Data Source
AI summary
The present disclosure provides a semiconductor device, including a substrate, a fin over the substrate, wherein the fin extends along a primary direction, a gate over the fin, the gate extends along the secondary direction orthogonal to the primary direction, a first conductive contact over the gate, and a conductive routing layer over the first conductive contact, wherein at least a portion of the fin is free from the coverage of a vertical projection of the conductive routing layer.