FinFET Cell-Row Termination Layout for Stable Edge Transistors
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Solution Overview
Problem
In semiconductor integrated circuits with fin transistors or nanowire FETs, the distance to adjacent transistors affects current and capacitance characteristics, leading to performance reduction and increased costs due to process-induced variations at cell row ends.
Innovation Solution
Incorporating cell-row-terminating cells with fins or nanowires that do not contribute to logical functions, these cells are designed to stabilize transistor characteristics by optimizing fin or nanowire placement and width, reducing process-induced variations and area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If standard cells are arranged in a standard cell system with fin transistors, then logical function is achieved, but transistor characteristics fluctuate due to varying distances to adjacent transistors
Solution Approach 1:
The patent applies preliminary action by introducing cell-row-terminating cells at the ends of cell rows before the actual logical function cells are arranged. These terminating cells are pre-configured with specific fin structures (such as fins extending beyond gate structures or overlapping patterns) to establish stable electrical characteristics at the cell row ends. This preliminary structural preparation ensures that when logical function cells are subsequently arranged, the transistor characteristics remain stable even though the distance to adjacent transistors varies, thereby resolving the contradiction between achieving logical function and maintaining reliability.
2Reliability
If margin is given to current and capacitance to account for cell arrangement variations, then transistor characteristic stability is improved, but circuit performance is reduced and cost increases
Solution Approach 1:
The patent applies local quality by creating non-uniform fin structures specifically at the cell row ends where stability is needed, rather than uniformly across all cells. The cell-row-terminating cells have fins with specific configurations (extending beyond gates or overlapping patterns) that are localized only at the ends of cell rows. This localized structural modification stabilizes transistor characteristics at critical positions without affecting the performance of the main logical function cells, thus improving reliability without sacrificing circuit performance or increasing cost.
3Reliability
If cell-row-terminating cells are added to stabilize transistor characteristics, then reliability is improved, but device area increases
Solution Approach 1:
The patent applies merging by integrating the cell-row-terminating cells into the standard cell row structure so that they occupy the same horizontal space as the logical function cells would. The terminating cells are designed with fin structures that utilize the available space efficiently, such as fins extending beyond gate structures or overlapping patterns, allowing the stabilization function to be achieved without significantly increasing the overall circuit block area. This merging approach combines the stabilizing function with the existing cell row layout, improving reliability while minimizing area increase.
Data Source
AI summary
A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.