FinFET Cell-Row Termination Layout for Stable Edge Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor integrated circuit devices using standard cells with fin transistors or nanowire FETs, the characteristics of fin transistors are significantly affected by the distance to adjacent transistors, leading to fluctuations in current and capacitance. This variability can result in reduced performance and increased costs due to the need for additional margins in design to accommodate these changes.
Innovation Solution
The introduction of cell-row-terminating cells at the ends of cell rows in the circuit block, which do not contribute to the logical function of the circuit block. These cells have fins or nanowires extending in a specific direction and gate structures arranged perpendicular to the cell rows, allowing for stabilization of transistor characteristics and reduction of process-induced variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard cells with fin transistors are arranged in a circuit block, then the performance of the semiconductor integrated circuit improves, but the transistor characteristics fluctuate due to varying distances to adjacent transistors
Solution Approach 1:
The patent applies local quality by creating different cell types with specific fin configurations at different locations. Cells at the end of cell rows are designed with fewer fins or different fin arrangements compared to cells in the middle, thereby adapting the local structure to compensate for the varying distance to adjacent transistors and stabilizing transistor characteristics at boundary locations.
Solution Approach 2:
The patent changes physical parameters of the fin structure, such as the number of fins, fin width, or fin spacing, in cells located at the end of cell rows. By adjusting these parameters, the patent compensates for the reduced shielding effect and stabilizes transistor characteristics despite the increased distance to adjacent transistors.
2Reliability
If margins are given to current and capacitance to accommodate characteristic changes, then transistor characteristic variations are covered, but the performance of the semiconductor integrated circuit reduces and cost increases
Solution Approach 1:
The patent takes preliminary action by designing cells with adjusted fin structures in advance, specifically at locations where characteristic variations are expected. This proactive structural adjustment eliminates the need for excessive design margins, thereby maintaining high circuit performance while ensuring reliable transistor characteristics.
3Reliability
If cell-row-terminating cells are introduced at the ends of cell rows, then transistor characteristics are stabilized and process-induced variations are reduced, but the area of the circuit block increases
Solution Approach 1:
The patent segments the circuit block into different cell types based on their location. Cells at the end of rows are segmented with different fin configurations compared to middle cells. This segmentation allows for targeted optimization of transistor characteristics without requiring excessive area, as only specific boundary cells are modified.
Solution Approach 2:
The cell-row-terminating cells serve multiple functions: they maintain the standard cell layout structure for area efficiency while simultaneously providing the modified fin configurations needed to stabilize transistor characteristics at boundary locations. This multi-functionality allows the patent to address characteristic stability without proportionally increasing the circuit block area.
Data Source
AI summary
A semiconductor integrated circuit device including standard cells including fin transistors includes, at a cell row end, a cell-row-terminating cell that does not contribute to a logical function of a circuit block. The cell-row-terminating cell includes a plurality of fins extending in an X direction. Ends of the plurality of fins on the inner side of the circuit block are near a gate structure placed at a cell end and do not overlap with the gate structure in a plan view, and ends of the plurality of fins on an outer side of the circuit block overlap with any one of a gate structure in a plan view.