FinFET-RRAM 3D Integration for Semiconductor Miniaturization
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Solution Overview
Problem
Current semiconductor devices face challenges in miniaturization due to the separate integration of fin transistors and resistive random access memory (RRAM) structures, which limits the reduction of overall device size.
Innovation Solution
Combining a fin transistor with a RRAM by directly fabricating the RRAM on the fin structure or epitaxial layer of the fin transistor, electrically connecting it to the source/drain regions, allowing for a three-dimensional integration that reduces the overall size of the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If fin transistor and RRAM are separately integrated, then manufacturing process is simpler, but overall device size is larger
Solution Approach 1:
The patent merges the RRAM structure directly with the fin transistor by forming the RRAM lower electrode, resistive switching layer, and upper electrode within the same device footprint as the fin transistor. The RRAM active region is positioned to overlap with the fin structure, allowing simultaneous functionality of both components without requiring separate integration areas, thus reducing overall device size while maintaining manufacturability through unified processing steps.
2Area of stationary object
If RRAM is directly fabricated on fin structure, then device area is reduced, but manufacturing precision requirement increases
Solution Approach 1:
The patent segments the device into distinct functional regions: the fin transistor region with its gate, source, and drain, and the RRAM region with its lower electrode, resistive switching layer, and upper electrode. By spatially separating these functions while maintaining overlapping footprints, the design allows each component to be fabricated with standard precision requirements rather than requiring ultra-precise alignment, thus reducing device area without excessively increasing manufacturing difficulty.
3Productivity
If three-dimensional integration is implemented, then device compactness is enhanced, but process complexity increases
Solution Approach 1:
The patent implements three-dimensional integration by stacking the RRAM layers vertically over the fin transistor structure. The RRAM lower electrode is formed on the source/drain region, the resistive switching layer is deposited above it, and the upper electrode is positioned at the top, creating a vertical stack that utilizes the third dimension (height) to achieve compactness. This approach maintains planar process simplicity while achieving 3D integration benefits.
Data Source
AI summary
The present invention provides a semiconductor structure, the semiconductor structure includes a fin transistor (fin filed effect transistor, finFET) located on a substrate, the fin transistor includes a gate structure crossing over a fin structure, and at least one source/drain region. And a resistive random access memory (RRAM) includes a lower electrode, a resistance switching layer and a top electrode being sequentially located on the source/drain region and electrically connected to the fin transistor.