FinFET Manufacturing Using Sacrificial Gate Oxidation for Thermal Isolation

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Solution Overview

Problem

The reduction in size of semiconductor devices, particularly MOSFETs, leads to a short channel effect, deteriorating operation characteristics, and requires improved self-heating and electrical characteristics, which existing technologies have not adequately addressed.

Innovation Solution

A method of manufacturing semiconductor devices involving patterning a substrate to form active fins, forming sacrificial gates, oxidizing exposed portions to create insulation patterns, and epitaxially growing source/drain regions, which reduces the short channel effect and improves self-heating characteristics by forming insulation patterns between the active fin and the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If MOSFET size is reduced to increase integration density, then productivity and integration density are improved, but short channel effect increases causing deterioration of operation characteristics

Engineering Contradiction:
Improveintegration densityVSAvoidoperation characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The substrate is divided into active fin regions and isolation regions, with device isolation patterns formed between adjacent fins. This segmentation allows each fin to be independently controlled and isolated, reducing the negative effects of short channel phenomenon while maintaining high integration density through compact fin spacing.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Device isolation patterns are selectively formed in specific regions between adjacent active fins, creating local electrical isolation where needed. This local quality approach reduces short channel effect at critical interfaces while maintaining overall device performance and allowing continuous scaling of fin density for improved productivity.

Inventive Principle:
Principle #3Local quality

2Ease of manufacture

If continuous substrate structure is used, then manufacturing simplicity is maintained, but self-heating characteristics deteriorate

Engineering Contradiction:
Improvesubstrate structure simplicityVSAvoidself-heating characteristics
Core Design Contradiction:
Ease of manufactureVSTemperature

Solution Approach 1:

Device isolation patterns are formed between adjacent active fins before completing the entire fabrication process. This preliminary action creates thermal isolation structures in advance, preventing heat accumulation in the substrate while maintaining manufacturing simplicity through integration with standard fabrication sequences.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If device isolation patterns are formed between adjacent fins, then short channel effect is reduced, but manufacturing process complexity increases

Engineering Contradiction:
Improveshort channel effect controlVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The formation of device isolation patterns is merged with the existing fabrication process sequence, where isolation patterns are created using the same etching and deposition steps already required for fin formation and gate fabrication. This merging reduces overall manufacturing process complexity while achieving effective short channel effect control.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This method effectively reduces the short channel effect and enhances electrical characteristics by forming insulation patterns under the channel region and directly connecting source/drain regions to the substrate, improving the performance of fin field effect transistors.

Implementation Method 1

oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate

Methodology Applied
Scientific EffectOxidation: Oxidation

Implementation Method 2

growing an epitaxial layer from the exposed substrate to form source/drain regions

Methodology Applied
Scientific EffectEpitaxy: Epitaxy

Data Source

PatentUS9276087B2Methods of manufacturing FINFET semiconductor devices using sacrificial gate patterns and selective oxidization of a fin
Publication Date: 2016.03.01 SAMSUNG ELECTRONICS CO LTD
  • US9276087B2 patent drawing
  • US9276087B2 patent drawing
  • US9276087B2 patent drawing

AI summary

A method of manufacturing a semiconductor device includes patterning a substrate to form an active fin, forming a sacrificial gate pattern crossing over the active fin on the substrate, forming an interlayer insulating layer on the sacrificial gate pattern, removing the sacrificial gate pattern to form a gap region exposing the active fin in the interlayer insulating layer, and oxidizing a portion of the active fin exposed by the gap region to form an insulation pattern between the active fin and the substrate.