FinFET Gate Stack Formation Using Sacrificial Spacer Template
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Solution Overview
Problem
Conventional methods for manufacturing FinFETs face challenges in forming small-sized gates along the length of semiconductor fins, leading to difficulties in controlling carriers and suppressing the short-channel effect, particularly as device sizes decrease.
Innovation Solution
The method involves forming a semiconductor fin with a trapezoid cross-section, using a sacrificial spacer to create a gate stack with a reduced thickness, and aligning the gate stack with source and drain regions, thereby reducing the need for complex photolithography and masks, and allowing for a shorter gate length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography is used to form the gate stack, then the manufacturing process is well-established, but the gate size cannot be reduced sufficiently to suppress the short-channel effect
Solution Approach 1:
A sacrificial spacer is formed in advance on the semiconductor fin before gate stack formation. This preliminary structure serves as a template that defines the gate length, enabling precise gate dimension control without relying on conventional photolithography. The sacrificial spacer is formed conformally and then anisotropically etched to create the precise length dimension needed for small gate sizes.
Solution Approach 2:
The sacrificial spacer acts as an intermediary object that temporarily occupies the space where the gate stack will eventually be formed. It mediates the relationship between the semiconductor fin and the gate stack by providing a physical template for alignment and dimension control. After the gate stack is formed using the spacer as a mask, the sacrificial spacer is removed, having served its purpose as a dimensional reference.
2Reliability
If the gate length is reduced to suppress short-channel effect, then carrier control improves, but the manufacturing difficulty increases significantly
Solution Approach 1:
The sacrificial spacer is formed beforehand with the precise thickness that corresponds to the desired gate length. This preliminary dimensioning allows the gate to achieve the small size needed for good carrier control while using standard manufacturing processes. The spacer's thickness, controlled by conformal deposition, directly determines the gate length without requiring complex lithography.
Solution Approach 2:
The invention changes the controlling parameter for gate length from photolithographic linewidth (which has resolution limits) to thin film deposition thickness (which can be controlled more precisely). By using conformal deposition of the sacrificial spacer, the gate length is controlled by the spacer thickness parameter, which can be precisely adjusted to achieve the required small gate dimensions for suppressing short-channel effects.
3Length of moving object
If a sacrificial spacer is used to form the gate stack, then the gate length can be reduced, but additional etching steps are introduced
Solution Approach 1:
The etching process is made selective and localized by using the sacrificial spacer as a mask. The anisotropic etching removes material only in regions not protected by the spacer, allowing precise gate length definition. The semiconductor fin is protected from damage in areas where the spacer provides coverage, while controlled etching occurs only where needed to define the gate region.
Solution Approach 2:
The sacrificial spacer serves as a protective intermediary during the etching process. It shields the semiconductor fin from excessive etching damage while allowing controlled removal of material to define the gate length. The spacer absorbs the harsh etching conditions, protecting the underlying fin structure from damage while still enabling the necessary dimensional control.
Data Source
AI summary
A FinFET and a method for manufacturing the same are disclosed. In one aspect, the method comprises forming a semiconductor fin having trapezoid cross-section. The method also includes forming one of a source region and a drain region. The method also includes forming a sacrificial spacer. The method also includes forming another one of the source region and the drain region using the sacrificial spacer as a mask. The method also includes removing the sacrificial spacer. The method also includes forming a gate stack in place of the sacrificial spacer, the gate stack comprising a gate conductor and a gate dielectric isolating the gate conductor from the semiconductor fin.