FinFET Circuit Design Using Dynamic Schematic Parasitic Simulation
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Solution Overview
Problem
Circuit designers face challenges in accurately simulating the performance of FinFET-based circuits due to the increasing impact of resistance and capacitance as node sizes decrease, requiring the use of artificial elements in separate schematics, which complicates the design process and increases resource consumption.
Innovation Solution
The method involves using a macro FinFET library that includes artificial elements to simulate resistance and capacitance effects, allowing for a single schematic design that can switch between parasitic and layout modes, enabling more accurate pre- and post-layout simulations without double-counting parasitic RC values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two separate schematics are used (one with artificial elements for RC simulation, another without for layout), then simulation accuracy is improved, but design complexity and time consumption increase
Solution Approach 1:
The patent implements a dynamic schematic system where artificial elements can be selectively included or excluded based on the simulation phase. The schematic transitions between including artificial elements for RC extraction and excluding them for layout verification, allowing a single schematic to serve multiple purposes at different stages of the design process.
Solution Approach 2:
The patent creates a universal schematic that can perform multiple functions: it can include artificial elements for accurate RC simulation when needed, and exclude them for clean layout verification when appropriate. This multi-functional approach eliminates the need for maintaining separate schematics while preserving simulation accuracy where required.
2Reliability
If iterative refinement of separate schematics is performed, then performance requirements are satisfied, but resource consumption and design time increase
Solution Approach 1:
The dynamic inclusion/exclusion of artificial elements allows the design process to progress efficiently through different stages without requiring repeated iterative refinement of separate schematics. The system adapts its configuration based on the current design phase, reducing unnecessary iterations.
Solution Approach 2:
The patent performs RC extraction and simulation with artificial elements in advance during the schematic design phase. This preliminary action allows performance requirements to be satisfied before layout finalization, reducing the need for later iterative adjustments and saving design time.
3Measurement precision
If artificial elements are included in the schematic, then RC performance is accurately simulated, but the risk of double-counting parasitic RC values increases
Solution Approach 1:
The system dynamically controls the inclusion of artificial elements based on the simulation phase. During RC extraction, artificial elements are included for accurate simulation. During subsequent layout verification, artificial elements are excluded to prevent double-counting. This dynamic control ensures both accuracy and reliability at different stages.
Solution Approach 2:
The patent implements a feedback mechanism that tracks whether artificial elements have been included in previous simulations. This feedback prevents double-counting by ensuring artificial elements are only included when necessary and are properly excluded in subsequent phases where their effects would be redundant.
Data Source
AI summary
A method of designing a fin field effect transistor (FinFET)-based circuit includes designing, using a processor, a first circuit schematic design based on a performance specification, the first circuit schematic design is free of artificial elements, wherein the artificial elements are used to simulate electrical performance of the FinFET-based circuit. The method further includes modifying, using the processor, at least one device within the first circuit schematic design to form a second circuit schematic design taking the artificial elements into consideration. The method further includes performing a pre-layout simulation using the second circuit schematic and taking the artificial elements into consideration. The method further includes generating a layout, wherein the layout does not take the artificial elements into consideration, and performing a post-layout simulation, wherein the post-layout simulation does not take the artificial elements into consideration.