FinFET Source/Drain Regions with Air Gaps for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor devices, particularly MOSFETs, are scaled down, their operating characteristics deteriorate due to high integration density, leading to limitations in performance improvement.
Innovation Solution
A semiconductor device design featuring active patterns protruding from a substrate with a gate structure intersecting them, source/drain regions, and contacts, where the source/drain regions have specific geometric configurations and materials with varying lattice constants, and device isolation patterns with recess regions and air gaps to optimize electrical characteristics and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFETs are scaled down to increase integration density, then device quantity increases, but operating characteristics deteriorate
Solution Approach 1:
The patent transitions from planar MOSFETs to three-dimensional FinFETs by creating vertical fin structures protruding from the substrate. This dimensional change increases the effective channel area and gate control without increasing the planar footprint, thereby maintaining integration density while improving operating characteristics through enhanced gate control and reduced short-channel effects
Solution Approach 2:
The channel region is segmented into multiple vertical fins instead of a single planar channel. Each fin acts as an independent current path with its own gate control, allowing the total channel width to be distributed across multiple segments. This segmentation improves gate control efficiency and reduces parasitic effects while maintaining high integration density
2Reliability
If source/drain contacts are positioned to connect source/drain regions, then electrical connection is established, but parasitic capacitance increases
Solution Approach 1:
An air gap is introduced as an intermediary between the source/drain contact and the active pattern. This air gap acts as a dielectric spacer that electrically isolates the contact from the active region, reducing parasitic capacitance while still allowing the contact to connect to the source/drain region through the air gap medium
Solution Approach 2:
The air gap creates a porous or void space between the source/drain contact and the active pattern. This void space reduces the dielectric constant in the region between the contact and active region, thereby reducing parasitic capacitance while maintaining the electrical connection path through the source/drain region
3Ease of manufacture
If source/drain regions have uniform width, then manufacturing is simplified, but electrical characteristics are suboptimal
Solution Approach 1:
The source/drain region is designed with non-uniform width where the width varies at different portions. The first portion has a different width than the second portion, allowing optimization of electrical characteristics such as current density distribution and resistance. This local variation in geometry improves electrical performance while remaining manufacturable through standard lithography and etching processes
Data Source
AI summary
A semiconductor device includes a plurality of active patterns protruding from a substrate, a gate structure intersecting the plurality of active patterns, a plurality of source/drain regions respectively on the plurality of active patterns at opposite sides of the gate structure, and source/drain contacts intersecting the plurality of active patterns, each of the source/drain contacts connected in common to the source/drain regions thereunder, each of the plurality of source/drain regions including a first portion in contact with a top surface of the active pattern thereunder, the first portion having a width substantially increasing as a distance from the substrate increases, and a second portion extending from the first portion, the second portion having a width substantially decreasing as a distance from the substrate increases, bottom surfaces of the source/drain contacts being lower than an interface between the first and second portions.