FinFET Source/Drain Contact Structure for Scalable Vertical Transistors
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Solution Overview
Problem
Existing vertical field-effect transistors have not been satisfactory in all aspects, particularly in terms of performance and scalability as the semiconductor industry continues to advance.
Innovation Solution
A method of fabricating a semiconductor component involving the formation of fins on a substrate, followed by the deposition of a dielectric layer and a capping layer, and the creation of gate structures and epitaxial layers to enhance carrier mobility and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar metal-oxide-semiconductor field-effect transistors are used, then manufacturing simplicity is maintained, but device performance and scalability deteriorate
Solution Approach 1:
The patent transitions from conventional planar (2D) transistor structures to vertical (3D) FinFET structures by adding the vertical dimension. The fin structure extends vertically from the substrate, enabling current flow in three dimensions and significantly improving device performance and scalability while maintaining manufacturing feasibility through established semiconductor processes.
2Productivity
If feature size is decreased to increase device density, then productivity is improved, but manufacturing precision requirements worsen
Solution Approach 1:
By moving to vertical FinFET structures, the patent achieves higher device density without proportionally decreasing horizontal feature sizes. The vertical extension of fins allows increased effective channel area while maintaining manufacturable lateral dimensions, thus improving productivity without excessively tightening manufacturing precision requirements.
Solution Approach 2:
The patent employs multiple nested layers including fins embedded in substrate, gate structures wrapping around fin tops, dielectric layers surrounding fins, and epitaxial layers coating fin surfaces. This nested architecture achieves high device density while each layer can be formed using standard semiconductor processes with manageable precision requirements.
3Reliability
If vertical field-effect transistors are implemented to improve performance, then device performance is improved, but scalability and reliability worsen
Solution Approach 1:
The patent creates a universal vertical FinFET platform that can be scaled across different device sizes and integrated into various circuit configurations. The standardized fin formation, gate wrapping, and epitaxial layer processes enable the same structural approach to be applied universally across different technology nodes and device types, ensuring both performance improvement and scalability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described method improves the performance and scalability of semiconductor components by enhancing carrier mobility and device reliability, addressing the limitations of existing vertical field-effect transistors.
Implementation Method 1
an epitaxial layer disposed on a sidewall of the fin
Data Source
AI summary
A semiconductor device includes a semiconductor fin, a gate structure, source/drain structures, and a contact structure. The semiconductor fin extends from a substrate. The gate structure extends across the semiconductor fin. The source/drain structures are on opposite sides of the gate structure. The contact structure is over a first one of the source/drain structures. The contact structure includes a semiconductor contact and a metal contact over the semiconductor contact. The semiconductor contact has a higher dopant concentration than the first one of the source/drain structures. The first one of the source/drain structures includes a first portion and a second portion at opposite sides of the fin and interfacing the semiconductor contact.