FinFET Source/Drain Curved Sidewalls and Sacrificial Layer Isolation

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Solution Overview

Problem

In the manufacturing of fin-type field effect transistors (finFETs), neighboring active fins can have source/drain layers that contact each other, leading to electrical shorts due to their proximity, compromising the electrical isolation and reliability of the semiconductor device.

Innovation Solution

The semiconductor device design includes a source/drain layer with curved sidewalls that have a decreasing slope from the bottom to the top, and a sacrificial layer with air gaps between active fins, allowing for selective epitaxial growth to form isolated source/drain layers, ensuring electrical insulation between adjacent fins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If active fins are placed close to each other to increase device density, then productivity is improved, but source/drain layers on neighboring active fins contact each other causing electrical shorts and reliability deteriorates

Engineering Contradiction:
Improvedevice densityVSAvoidelectrical isolation
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A sacrificial layer is formed between adjacent active fins before forming the source/drain layers. This preliminary placement of the sacrificial layer prevents direct contact between source/drain layers on neighboring fins, ensuring electrical isolation is maintained even when fins are closely spaced to increase device density.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer acts as an intermediary material positioned between adjacent active fins. During selective epitaxial growth, this intermediary layer prevents the source/drain material from bridging between neighboring fins, thereby maintaining electrical isolation while allowing high device density.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If selective epitaxial growth is performed to form isolated source/drain layers, then reliability is improved through electrical isolation, but manufacturing complexity increases due to additional process steps

Engineering Contradiction:
Improveelectrical isolationVSAvoidmanufacturing process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The sacrificial layer is formed in advance between active fins, creating a pre-configured structure that guides subsequent selective epitaxial growth. This preliminary preparation simplifies the overall manufacturing process by establishing isolation regions before source/drain formation, rather than requiring complex post-processing steps.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The sacrificial layer automatically defines the growth regions for source/drain layers during selective epitaxial growth. The process self-organizes around the sacrificial layer structure, with material growing only in regions not occupied by the sacrificial layer, thereby simplifying control of the manufacturing process while ensuring reliable electrical isolation.

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design effectively prevents electrical shorts between neighboring active fins, enhancing the reliability and electrical isolation of the semiconductor device by forming isolated source/drain layers through selective epitaxial growth.

Implementation Method 1

a selective epitaxial growth (SEG) process may be performed to form source/drain layers filling the recesses

Methodology Applied
Scientific EffectSelective epitaxial growth: Epitaxy

Data Source

PatentUS10242917B2Semiconductor devices including active fins and methods of manufacturing the same
Publication Date: 2019.03.26 SAMSUNG ELECTRONICS CO LTD
  • US10242917B2 patent drawing
  • US10242917B2 patent drawing
  • US10242917B2 patent drawing

AI summary

Semiconductor devices may include a plurality of active fins each extending in a first direction on a substrate, a gate structure extending on the active fins in a second direction, and a first source/drain layer on first active fins of the active fins adjacent the gate structure. At least one of two opposing sidewalls of a cross-section of the first source/drain layer taken along the second direction may include a curved portion having a slope with respect to an upper surface of the substrate. The slope may decrease from a bottom toward a top thereof.