FinFET Source/Drain Recess Formation via Sacrificial Layer Etching
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Solution Overview
Problem
The scaling down of MOSFETs in semiconductor devices has led to performance deterioration, necessitating improved methods for forming integrated circuit devices with enhanced density and electrical characteristics.
Innovation Solution
A method involving the formation of a gate structure on a substrate, followed by the creation of etch masks and recesses, where a sacrificial layer is etched and removed to form source/drain recesses, allowing for the growth of source/drain regions with specific geometries that improve the interface between the active fin and source/drain regions, enhancing the semiconductor device's electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MOSFET sizes are scaled down to increase device density, then device density increases, but electrical performance deteriorates
Solution Approach 1:
The patent transitions from planar MOSFETs to three-dimensional FinFETs by creating vertical fin structures through anisotropic etching. This dimensional change increases the effective channel area and improves electrical performance without further scaling the lateral dimensions, thereby maintaining device density while recovering electrical characteristics.
Solution Approach 2:
The patent introduces a sacrificial layer (silicon germanium) as an intermediary material during the formation process. This sacrificial layer enables precise control of source/drain recess geometry and facilitates the formation of high-quality interfaces between the fin and source/drain regions, improving electrical performance.
2Ease of manufacture
If conventional etching methods are used to form source/drain recesses, then manufacturing process is simple, but junction profile uniformity is poor
Solution Approach 1:
The sacrificial silicon germanium layer acts as a mediator that enables precise junction profile control. By etching this sacrificial layer selectively, the patent achieves uniform source/drain recesses with controlled depths and widths, improving junction profile uniformity while maintaining process feasibility.
Solution Approach 2:
The patent performs preliminary formation of source/drain recesses using the sacrificial layer before final source/drain material deposition. This preliminary action ensures uniform recess geometries and facilitates subsequent material filling, achieving both manufacturing precision and ease of manufacture.
3Reliability
If source/drain regions are formed with larger volumes, then electrical performance improves, but device area increases
Solution Approach 1:
The patent forms source/drain regions with significant vertical extent by etching deep recesses into the substrate and filling them with source/drain material. This vertical expansion increases the effective source/drain volume and improves electrical performance without increasing the lateral device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved electrical characteristics and increased volumes of source/drain regions, leading to enhanced performance and uniform junction profiles in semiconductor devices.
Implementation Method 1
anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate
Implementation Method 2
etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask
Data Source
AI summary
Methods of forming an integrated circuit device are provided. The methods may include forming a gate structure on a substrate, forming a first etch mask on a sidewall of the gate structure, anisotropically etching the substrate using the gate structure and the first etch mask as an etch mask to form a preliminary recess in the substrate, forming a sacrificial layer in the preliminary recess, forming a second etch mask on the first etch mask, etching the sacrificial layer and the substrate beneath the sacrificial layer using the gate structure and the first and second etch masks as an etch mask to form a source/drain recess in the substrate, and forming a source/drain in the source/drain recess. A sidewall of the source/drain recess may be recessed toward the gate structure relative to an outer surface of the second etch mask.