FinFET Diffusion Breaks via Replacement Gate Process

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Solution Overview

Problem

The formation of single and double diffusion breaks in FinFET devices is challenging due to the loss of desired stress profiles when fins are cut prior to gate structure formation, and existing methods for forming isolation structures consume valuable substrate space, leading to reduced packing densities and increased complexity.

Innovation Solution

The method involves forming single and double diffusion break structures using a replacement gate process, where a single fin-cut masking layer is used to create both SDB and DDB isolation structures, reducing processing complexity and maintaining stress profiles by aligning the fin cuts with the gate structures, and using high-k insulating materials to fill trenches between active regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If fins are cut prior to gate structure formation to create diffusion breaks, then isolation structures can be formed, but the desired stress profiles are lost

Engineering Contradiction:
Improveisolation structure formationVSAvoidstress profile
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The gate structure is formed preliminarily before cutting the fins to create diffusion breaks. This preliminary gate formation serves as a reference structure that guides subsequent fin cutting, ensuring that the stress profile is maintained while still allowing isolation structures to be formed. The gate structure acts as a template that preserves the stress characteristics during the diffusion break creation process.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If traditional isolation structures are used, then electrical isolation between fins is achieved, but valuable substrate space is consumed

Engineering Contradiction:
Improveelectrical isolationVSAvoidsubstrate space
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The diffusion break structure merges the isolation function with the gate structure by forming the diffusion breaks within the gate structure footprint. This combining of functions allows electrical isolation between fins to be achieved without requiring separate, space-consuming isolation structures, thereby maximizing substrate space utilization while maintaining reliability.

Inventive Principle:
Principle #5Merging (Combining)

3Manufacturing precision

If multiple masking layers are used to form SDB and DDB structures, then precise isolation is achieved, but processing complexity increases

Engineering Contradiction:
Improveisolation precisionVSAvoidprocessing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

A single masking layer is designed to serve multiple functions: it defines both the single diffusion break (SDB) and double diffusion break (DDB) regions, and also serves as the gate structure definition layer. This multi-functional masking approach achieves precise isolation for both SDB and DDB structures while significantly reducing processing complexity by eliminating the need for multiple separate masking steps.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9865704B2Single and double diffusion breaks on integrated circuit products comprised of FinFET devices
Publication Date: 2018.01.09 GLOBALFOUNDRIES US INC
  • US9865704B2 patent drawing
  • US9865704B2 patent drawing
  • US9865704B2 patent drawing

AI summary

One illustrative integrated circuit product disclosed herein includes, among other things, a plurality of FinFET devices, each of which comprises a gate structure comprising a high-k gate insulation material and at least one layer of metal, a single diffusion break (SDB) isolation structure positioned in a first trench defined in a semiconductor substrate between first and second active regions, the SDB isolation structure comprising the high-k insulating material and the at least one layer of metal, and a double diffusion break (DDB) isolation structure positioned in a second trench defined in a semiconductor substrate between third and fourth active regions, the DDB isolation structure comprising a first insulating material that substantially fills the second trench.