FinFET SDB Gate Isolation Structure for Threshold Voltage Control
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Solution Overview
Problem
Current FinFET fabrication processes face challenges in integrating single diffusion break (SDB) structures and metal gate fabrication, particularly in controlling the gate and fin-shaped structure overlap, which affects the channel region and threshold voltage.
Innovation Solution
A method involving forming fin-shaped structures on a substrate, creating trenches to divide them into portions, and filling dielectric layers in these trenches to form SDB and gate isolation structures, with specific steps including forming a gate layer, removing parts to create trenches, and depositing dielectric material, followed by planarization to achieve the desired structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shallow trench isolation (STI) is formed around the fin-shaped structure and part of the STI is removed to form a trench, then single diffusion break (SDB) structure or isolation structure can be formed, but the integration of the SDB structure and metal gate fabrication still remains numerous problems
Solution Approach 1:
The patent divides the fin-shaped structure into multiple portions using trenches, creating separate regions for different functions. The fin-shaped structure is segmented into a first portion and a second portion by forming a trench between them, allowing independent control and fabrication processes for each segment, thereby simplifying the integration of SDB structure and metal gate fabrication
Solution Approach 2:
The patent applies different properties to different parts of the structure. The gate layer is selectively removed from between the first and second portions of the fin-shaped structure, creating a localized region with different electrical properties. This allows the SDB structure to have specific characteristics in certain regions while maintaining other properties in different regions, resolving the integration complexity
2Reliability
If the gate and fin-shaped structure overlapping area is increased to enhance channel region control, then the channel region can be more effectively controlled and current increased, but the fabrication process complexity increases
Solution Approach 1:
The gate structure is segmented into different regions with varying overlap areas. The gate layer is selectively removed from between the first and second portions of the fin-shaped structure, creating regions with different gate-fin overlapping areas. This segmentation allows optimization of channel control in specific regions while simplifying the overall fabrication process
Solution Approach 2:
Instead of increasing the gate overlap area uniformly across the entire fin structure, the patent selectively removes the gate layer from specific regions between fin portions. This inverted approach achieves effective channel control by creating localized high-overlap regions while reducing complexity through selective removal rather than universal expansion
Data Source
AI summary
A semiconductor device includes a gate structure on a substrate, a single diffusion break (SDB) structure adjacent to the gate structure, a first spacer adjacent to the gate structure, a second spacer adjacent to the SDB structure, a source/drain region between the first spacer and the second spacer, an interlayer dielectric (ILD) layer around the gate structure and the SDB structure, and a contact plug in the ILD layer and on the source/drain region. Preferably, a top surface of the second spacer is lower than a top surface of the first spacer.