FinFET Vertical SDB Isolation Structure for Short-Channel Reliability

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Integrated circuit devices face challenges in maintaining high integration and reliability due to short channel effects, which degrade as they are downscaled, and existing isolation structures fail to provide complete isolation between adjacent device regions, leading to contact defects and reduced reliability.

Innovation Solution

The integrated circuit device incorporates a substrate with fin-type active areas, channel structures, gate lines, and a single diffusion break (SDB) isolation structure that extends vertically through the substrate, ensuring complete isolation between device regions by overlapping with gate lines and source/drain regions, thereby enhancing inter-device isolation reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional isolation structures are used, then device integration is maintained, but isolation reliability degrades due to incomplete separation between adjacent device regions

Engineering Contradiction:
Improveisolation reliabilityVSAvoidisolation structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The isolation structure transitions from a planar configuration to a vertical three-dimensional structure that passes completely through the substrate thickness direction. This vertical extension enables complete isolation between adjacent device regions by blocking diffusion paths in the depth dimension, thereby improving isolation reliability without increasing lateral device complexity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The substrate is divided into distinct isolated regions by the vertically extending isolation structure. This segmentation creates complete separation between adjacent device regions, preventing electrical interference and contact defects while maintaining clear device boundaries

Inventive Principle:
Principle #1Segmentation

2Productivity

If device downscaling is pursued, then integration density increases, but short channel effects worsen and reliability degrades

Engineering Contradiction:
Improveintegration densityVSAvoidtransistor reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The isolation structure extends vertically through the substrate thickness, adding a depth dimension to isolation. This vertical configuration provides complete separation between adjacent transistors even at scaled dimensions, preventing short channel effects and maintaining reliability while allowing continued integration density improvements

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Reliability

If vertical isolation structures are implemented, then complete isolation between device regions is achieved, but manufacturing precision requirements increase

Engineering Contradiction:
Improveinter-device isolationVSAvoidisolation structure alignment
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The vertical isolation structure serves multiple functions simultaneously: it provides complete isolation between adjacent device regions, acts as a diffusion barrier, and establishes clear device boundaries. This multi-functionality achieves superior isolation reliability through a single integrated structure rather than multiple separate components requiring precise alignment

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS20240387624A1Integrated circuit device
Publication Date: 2024.11.21 SAMSUNG ELECTRONICS CO LTD
  • US20240387624A1 patent drawing
  • US20240387624A1 patent drawing
  • US20240387624A1 patent drawing

AI summary

An integrated circuit device includes a substrate including a first surface and a second surface that are opposite to each other, a fin type active area extending from the first surface of the substrate in a first direction, a channel structure on an upper surface of the fin type active area and including a channel region, a source/drain region on the upper surface of the fin type active area, a gate line extending on the substrate in a second direction that is perpendicular to the first direction, disposed on the substrate, and surrounding the channel structure, and an isolation structure passing vertically through the substrate and the fin type active area and located at one side of the source/drain region, wherein the channel structure, the source/drain region, and the isolation structure are sequentially arranged in the first direction.