FinFET SDB Isolation Liner for Contact Reliability
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Solution Overview
Problem
As fin-type field effect transistor (FINFET) size decreases and density increases, it becomes challenging to form FINFETs without compromising robustness, leading to difficulties in forming source/drain contacts due to angled top surfaces of the source/drain regions, which can result in unlanded contacts and defective devices.
Innovation Solution
The method involves forming single-diffusion break (SDB) type isolation regions within the semiconductor fin with a semiconductor liner, ensuring that the source/drain recesses have semiconductor surfaces for epitaxial growth, minimizing the angle of the top surface of the source/drain region relative to the fin surface and reducing the risk of unlanded contacts by providing exposed semiconductor surfaces for epitaxial deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FINFET size is decreased and density is increased, then device scalability and density are improved, but manufacturing robustness deteriorates due to difficulties in forming source/drain contacts
Solution Approach 1:
A semiconductor liner layer is deposited onto the isolation region surface before forming source/drain recesses. This preliminary action ensures that when recesses are etched, the liner remains as a thin residual layer at the recess bottom, providing a semiconductor surface for epitaxial growth even in scaled devices. This pre-prepared surface structure enables reliable source/drain region formation in high-density FINFETs where robustness would otherwise be compromised.
Solution Approach 2:
The semiconductor liner acts as an intermediary between the isolation region and the source/drain recess. Instead of directly exposing the isolation material (which would create angled surfaces problematic for contact formation), the liner provides a intermediate semiconductor surface that facilitates proper epitaxial growth. This mediator layer resolves the conflict between maintaining isolation integrity and enabling reliable source/drain contact formation in scaled devices.
2Ease of manufacture
If source/drain recesses are formed adjacent to isolation regions without a semiconductor liner, then manufacturing process is simplified, but the top surface of source/drain regions becomes angled causing unlanded contacts
Solution Approach 1:
The semiconductor liner is deposited onto the isolation region surface before recess formation. This preliminary coating ensures that when anisotropic etching creates the recess, the liner etches at a different rate or provides a stop layer, leaving a thin residual semiconductor layer at the recess bottom. This pre-established semiconductor surface prevents the formation of angled top surfaces on source/drain regions, ensuring contacts land properly on flat surfaces.
Solution Approach 2:
The introduction of the semiconductor liner changes the etching parameters and surface properties at the isolation region interface. The liner layer modifies how the etch front progresses, creating a different etch profile that results in a flatter top surface for the source/drain region. This parameter change (adding the liner layer) transforms the geometric outcome from an angled surface to a minimal-angle surface suitable for contact formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the risk of unlanded source/drain contacts by ensuring that the epitaxial semiconductor material grows on both sides of the source/drain recess, including the trench isolation region, thereby maintaining a minimal angle with the fin surface, enhancing contact reliability and device robustness.
Implementation Method 1
source/drain regions can be formed by epitaxially depositing an additional semiconductor layer in the source/drain recesses
Data Source
AI summary
Disclosed is a method of forming a semiconductor structure that includes one or more fin-type field effect transistors (FINFETs) and single-diffusion break (SDB) type isolation regions that are within a semiconductor fin and that define the active device region(s) for the FINFET(s). The isolation regions are formed so that they include a semiconductor liner. The semiconductor liner ensures that, when a source/drain recess is formed immediately adjacent to the isolation region, the bottom and opposing sides of the source/drain recess will have semiconductor surfaces onto which epitaxial semiconductor material for a source/drain region is grown. As a result, the angle of the top surface of the source/drain region relative to the top surface of the semiconductor fin is minimized. Thus, the risk that a subsequently formed source/drain contact will not reach the source/drain region is also minimized. Also disclosed is a semiconductor structure formed according to the method.