FinFET Seal Ring Monitoring Pattern for Thicker Epitaxy
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Solution Overview
Problem
The existing manufacturing processes for semiconductor integrated circuits with fin field-effect transistors (finFETs) face challenges in achieving efficient epitaxial growth of source and drain structures, leading to insufficient thickness and high electrical resistance due to limited growth directions, which affects device performance and reliability.
Innovation Solution
The introduction of dummy polycrystalline silicon structures around the monitoring pattern fins promotes epitaxial growth in multiple directions, increasing the thickness of the epitaxial material and improving electrical contact, by forming these structures concurrently with the finFET gates and seal rings during the same manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional manufacturing processes are used for finFET source and drain structures, then the manufacturing process is simple, but the epitaxial growth thickness is insufficient and electrical resistance is high
Solution Approach 1:
The patent introduces dummy polysilicon structures that enable epitaxial growth in multiple directions (upward from fin top and laterally from dummy structure sides) instead of the conventional single upward direction. This dimensional expansion of growth directions increases the effective epitaxial growth thickness and improves electrical contact without fundamentally changing the manufacturing process complexity
Solution Approach 2:
The dummy polysilicon structures act as intermediary elements that facilitate enhanced epitaxial growth. These structures are formed concurrently with finFET gates and seal rings, serving as temporary mediators that promote multi-directional material deposition and improve electrical contact between source/drain regions and metallization layers
2Reliability
If conventional epitaxial growth is used with limited growth directions, then the manufacturing process is straightforward, but electrical resistance remains high
Solution Approach 1:
By adding lateral epitaxial growth directions from the sides of dummy polysilicon structures to the conventional upward growth direction, the patent creates multiple growth pathways. This multi-directional approach ensures better electrical contact quality and reduces resistance while maintaining process simplicity through concurrent formation with existing structures
3Manufacturing precision
If dummy polysilicon structures are added to promote multi-directional epitaxial growth, then epitaxial thickness and electrical contact improve, but device structure becomes more complex
Solution Approach 1:
The dummy polysilicon structures are merged with the existing manufacturing process by being formed concurrently with finFET gates and seal rings. This integration approach adds the necessary structural complexity for improved epitaxial growth without requiring separate processing steps, thereby minimizing the net increase in device complexity
Solution Approach 2:
The dummy polysilicon structures serve multiple functions: they act as templates for lateral epitaxial growth, provide structural support during processing, and facilitate electrical contact formation. This multi-functionality justifies the added structural complexity by delivering multiple benefits from a single structural addition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the epitaxial growth rate and thickness, reducing electrical resistance and improving the integrity of the semiconductor device, enabling better performance and reliability by facilitating effective contact with metallization layers.
Implementation Method 1
epitaxially growing an epitaxial material on the one or more monitoring pattern fins between the first and second polysilicon structures
Data Source
AI summary
An integrated circuit (IC) manufacturing method includes: forming, in a device region of the semiconductor wafer, fins of fin field-effect transistors (finFETs) of the IC; forming, in a seal ring region surrounding the device region, at least one seal ring comprising fins encircling the device region and a monitoring pattern comprising fins encircling the device region; and forming, in the device region, gates of the finFETs of the IC. Polysilicon structures are formed on the fins of the monitoring pattern in a connecting region of the monitoring pattern. An epitaxial material is grown on the fins of the monitoring pattern between the polysilicon structures by a combination of epitaxial growth upward from the fins and epitaxial growth inward from the polysilicon structures. At least one electrical contact is formed that electrically contacts the epitaxial material.