FinFET Source/Drain Sealing Structure for Low-Capacitance Stability
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Solution Overview
Problem
There is a need to improve the element performance and reliability of semiconductor devices, particularly in multi-gate transistors, by reducing capacitance and ensuring electrical stability as the pitch decreases, while maintaining current control capability and suppressing short channel effects.
Innovation Solution
The semiconductor device incorporates fin-shaped patterns with a field insulating layer and source/drain patterns, including a silicon-germanium pattern doped with a p-type impurity, and sealing insulating patterns to enhance electrical stability and reduce capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the pitch of the semiconductor device is decreased to increase density, then device density is improved, but capacitance increases and electrical stability deteriorates
Solution Approach 1:
The patent introduces a sealing insulating pattern as an intermediary element between the source/drain pattern and the surrounding environment. This sealing insulating pattern extends along the connection surface of the source/drain pattern and the upper surface of the field insulating layer, acting as a mediator that reduces parasitic capacitance while maintaining electrical stability. The sealing insulating pattern effectively isolates the high-density structure from unwanted electrical interactions, resolving the contradiction between increased density and maintained electrical stability.
2Productivity
If the pitch of the semiconductor device is decreased to increase density, then device density is improved, but capacitance increases
Solution Approach 1:
The sealing insulating pattern serves as an intermediary that reduces parasitic capacitance between closely spaced structures. By extending along the connection surface of the source/drain pattern and the field insulating layer, it creates electrical isolation that minimizes unwanted capacitive coupling, thereby reducing energy loss while maintaining high device density.
Solution Approach 2:
The patent modifies the structural parameters by introducing the sealing insulating pattern with specific geometric characteristics - extending along the connection surface and upper surface of the field insulating layer. This parameter change effectively reduces the parasitic capacitance without compromising the high-density layout, allowing the device to maintain both high density and low capacitance.
3Reliability
If multi-gate transistor structure is used to improve current control capability, then current control is improved, but device complexity increases
Solution Approach 1:
The patent employs a multi-gate transistor structure where the gate wraps around the channel in three dimensions, providing enhanced control over the current flow. This dimensional approach allows the gate to control the channel from multiple directions (top and sidewalls), improving current control capability while the integration into the existing fin-shaped pattern architecture helps manage the overall device complexity.
Data Source
AI summary
A semiconductor device including: a plurality of fin-shaped patterns spaced apart from each other in a first direction and extending in a second direction on a substrate; a field insulating layer covering sidewalls of the plurality of fin-shaped patterns and disposed between the fin-shaped patterns; a source/drain pattern connected to the plurality of fin-shaped patterns on the field insulating layer, the source/drain pattern including bottom surfaces respectively connected to the fin-shaped patterns, and at least one connection surface connecting the bottom surfaces to each other, and a sealing insulating pattern extending along the connection surface of the source/drain pattern and an upper surface of the field insulating layer, wherein the source/drain pattern includes a silicon-germanium pattern doped with a p-type impurity.