FinFET Gate Seed Layer Structure for Threshold Voltage Stability
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Solution Overview
Problem
The semiconductor industry faces challenges in shrinking the size and increasing the speed of Fin Field-Effect Transistors (FinFETs) while managing issues such as fluorine-induced threshold voltage shifts, which affect device performance and design flexibility.
Innovation Solution
A multi-layer seed layer with both crystalline and amorphous sublayers is used to reduce fluorine presence near the gate dielectric, allowing for improved interface formation and conductive material deposition, thereby reducing threshold voltage shifts and enhancing device design options.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET size is continuously shrunk to increase device density and speed, then device scaling and integration density are improved, but fluorine contamination causes threshold voltage shifts that degrade device reliability
Solution Approach 1:
The seed layer is divided into multiple sub-layers (first seed layer and second seed layer) with different structures (crystalline and amorphous). This segmentation allows each sub-layer to perform specific functions: the crystalline sub-layer provides structural stability while the amorphous sub-layer reduces fluorine contamination, thereby resolving the contradiction between device scaling and threshold voltage stability.
Solution Approach 2:
The invention uses a composite seed layer structure combining crystalline and amorphous materials. This composite approach leverages the advantages of both material states: the crystalline structure offers order and stability, while the amorphous structure provides flexibility and reduced fluorine interaction, thus maintaining reliability during device shrinkage.
2Ease of manufacture
If a single-structure seed layer is used for simplicity, then manufacturing process is easier, but fluorine contamination and Vt shifts cannot be effectively controlled
Solution Approach 1:
The seed layer fabrication process is segmented into multiple deposition steps, each creating a specific sub-layer structure. While this increases process steps, each step uses standard deposition techniques, making the complexity manageable. The segmentation enables precise control over fluorine contamination and threshold voltage, trading moderate process complexity for significant reliability improvement.
3Productivity
If device dimensions are reduced to increase integration, then device speed and density improve, but manufacturing precision requirements increase due to fluorine contamination control
Solution Approach 1:
The composite seed layer structure with crystalline and amorphous sub-layers provides inherent protection against fluorine contamination at the nanoscale. This material-level solution enables precise control of fluorine interactions without requiring extreme manufacturing precision, thus supporting continued device scaling while maintaining contamination control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The use of a seed layer with crystalline and amorphous sublayers reduces fluorine-induced threshold voltage shifts, offering greater flexibility in device design and performance by minimizing fluorine concentration, thus addressing the limitations of existing FinFET technologies.
Implementation Method 1
Employing a multi-layer seed layer with alternating crystalline and amorphous sublayers for the conductive gate structure to reduce fluorine presence and mitigate Vt shifts
Data Source
AI summary
A method includes forming a first semiconductor fin protruding from a substrate and forming a gate stack over the first semiconductor fin. Forming the gate stack includes depositing a gate dielectric layer over the first semiconductor fin, depositing a first seed layer over the gate dielectric layer, depositing a second seed layer over the first seed layer, wherein the second seed layer has a different structure than the first seed layer, and depositing a conductive layer over the second seed layer, wherein the first seed layer, the second seed layer, and the conductive layer include the same conductive material. The method also includes forming source and drain regions adjacent the gate stack.