FinFET Fabrication via Segmented Isolation Sequences
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in fabricating fin field effect transistors (FinFETs) due to difficulties in epitaxial structure integrity and varying epitaxial heights, leading to increased costs and complexity as device density increases, particularly in achieving precise fin structures and reducing processing loads.
Innovation Solution
A method is developed that integrates the isolation first and isolation last processes, where the isolation last process is performed in the logic area with smaller dimensions and the isolation first process in larger areas, such as ESD or peripheral regions, to form precise fin structures efficiently, involving steps like forming fin structures, epitaxial growth, and gate electrode formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fins are formed by epitaxially growing in-between isolation structure, then fin structures can be formed, but epitaxial structure integrity deteriorates as device density increases
Solution Approach 1:
The patent performs epitaxial growth before forming isolation structures (isolation-first approach). By growing the epitaxial fin structures first and then forming isolation regions around them, the method ensures that epitaxial growth occurs in a stable environment without the constraints of pre-formed isolation structures, thereby maintaining epitaxial structure integrity while achieving high device density
Solution Approach 2:
The patent inverts the conventional sequence of operations by forming epitaxial fin structures before isolation structures, rather than the traditional isolation-first approach. This inversion allows the epitaxial growth to proceed without interference from pre-formed isolation structures, resolving the contradiction between achieving precise fin structures and maintaining epitaxial integrity at high device densities
2Productivity
If fins are formed prior to isolation structures, then device density can be increased, but different heights of epitaxial structures occur requiring extra CMP processes
Solution Approach 1:
The patent applies different processing approaches to different regions of the substrate. In high-density logic regions, epitaxial fins are formed first followed by isolation structures. In large-area regions, conventional isolation-first approaches are used. This localized quality approach allows the method to achieve high device density where needed while avoiding unnecessary process complexity in other regions
Solution Approach 2:
The patent divides the semiconductor substrate into different processing zones (high-density logic regions and large-area regions) and applies different fin formation methodologies to each zone. This segmentation allows the isolation-first approach to be used only where high device density is required, thereby increasing productivity without unnecessarily increasing process complexity across the entire wafer
3Manufacturing precision
If extra CMP processes are added to equalize epitaxial heights, then uniformity is improved, but material and process costs increase
Solution Approach 1:
The patent performs epitaxial growth before isolation structure formation, which allows for more controlled and uniform epitaxial growth across the substrate. By establishing the fin structures first in a uniform manner and then forming isolation structures around them, the method achieves height uniformity without requiring additional CMP processes, thereby improving manufacturing precision while reducing manufacturing costs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for better integration of FinFETs in both logic and large areas, reducing extra processing and material costs while maintaining high device performance and density.
Implementation Method 1
forming an oxide layer on the substrate filling in-between the fin structures in the logic region
Implementation Method 2
forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region
Data Source
AI summary
The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.