FinFET Gate Formation via Segmented Spacer Layers
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Solution Overview
Problem
The sidewall-spacer process in finFET manufacturing can lead to angled fin sidewalls, narrowing the process window and causing conductive residue to form between adjacent gates, resulting in short circuits and reduced yields due to the conformal film thickening in gaps between fins.
Innovation Solution
A method involving the formation of deep-isolation and shallow trenches, followed by the creation of buffer, stop, and sacrificial regions, and the use of multiple spacer layers to define fin and gate structures, ensuring precise alignment and spacing to prevent conductive residue formation and enhance yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If a sidewall-spacer process is used to form gates, then narrower gates can be formed relative to photolithography, but conductive residue may form between adjacent gates causing short circuits
Solution Approach 1:
The patent divides the gate formation process into multiple discrete steps: forming sacrificial fins, depositing first spacers, removing sacrificial fins, depositing second spacers, and forming gates. This segmentation allows precise control over gate dimensions and spacing, preventing conductive residue formation while achieving narrow gate widths that single-step photolithography cannot provide
Solution Approach 2:
The patent performs preliminary actions by forming sacrificial fins and first spacers before actual gate formation. These preliminary structures define the precise locations and dimensions of future gates, ensuring proper spacing between adjacent gates before conductive materials are deposited, thereby preventing short circuits
2Ease of manufacture
If fins are formed with angled sidewalls, then the fin structure can be created, but the process window narrows and conformal film thickness increases in gaps causing residue formation
Solution Approach 1:
The patent introduces sacrificial fins and spacer layers as intermediary structures that mediate between the fin formation process and final gate creation. These intermediaries provide well-defined vertical surfaces for conformal film deposition, ensuring uniform film thickness even when underlying fins have angled sidewalls, thereby preventing residue formation while maintaining ease of manufacture
Solution Approach 2:
The patent changes the geometric parameters of intermediary structures (sacrificial fins and spacers) to compensate for angled fin sidewalls. By adjusting the dimensions and positions of these intermediaries, the process maintains precise control over final gate dimensions and spacing, ensuring uniform conformal film deposition regardless of underlying fin geometry
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of finFETs with reduced likelihood of short circuits and increased yield by maintaining precise control over fin and gate dimensions, improving the reliability and efficiency of the manufacturing process.
Implementation Method 1
the fins were formed with an etch that is less than perfectly anisotropic. These angled sidewalls can narrow, and in some cases close, the process window for the sidewall spacer.
Implementation Method 2
when the conformal film is deposited in this narrower gap, the portions of the film covering the adjacent sidewalls can join, creating a film with a larger vertical thickness in the gap.
Data Source
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AI summary
Disclosed are methods, systems and devices, including a method that includes the acts of etching an inter-row trench (144, 220) in a substrate (102, 210), substantially or entirely filling the inter-row trench (144, 220) with a dielectric material (150, 222), and forming a fin (190, 258) and an insulating projection (168, 242) at least in part by etching a gate trench (164, 238) in the substrate (102, 210). In some embodiments, the insulating projection (168, 242) includes at least some of the dielectric material (150, 222) in the inter-row trench (144, 220).