Selective Deposition for FinFET Spacer Formation
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Solution Overview
Problem
FinFET fabrication faces challenges due to the topography induced by the crossing of fin structures with gate structures, leading to fabrication difficulties and a need for more manufacturable methods.
Innovation Solution
A laterally selective deposition method using a vertical sidewall activated mandrel layer on a horizontal surface passivated substrate, where a spacer layer is formed adjacent to the gate electrode but does not cover the entire sidewall of the semiconductor fin, allowing for the growth of material layers only on the sidewall of the mandrel layer and not on the substrate surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a gate electrode of considerable thickness is formed upon a semiconductor fin that is scaled to considerable height, then the finFET device performance is enhanced, but topography is induced that provides fabrication difficulties
Solution Approach 1:
The patent applies preliminary action by forming a mandrel layer on the substrate before forming the gate electrode. This mandrel layer serves as a preparatory structure that enables subsequent selective deposition processes. The mandrel layer is formed in advance to create the necessary topography control features that will guide the gate electrode formation, thereby resolving the fabrication difficulty caused by the topography induced by thick gate electrodes on high fins.
Solution Approach 2:
The patent applies local quality through selective deposition where different regions of the substrate receive different treatments. Specifically, certain areas are made reactive to deposition while other areas are rendered non-reactive, allowing the gate electrode material to be deposited selectively only where needed. This local differentiation enables precise control over gate electrode formation in the context of fin topography, improving manufacturability without compromising device performance.
2Device complexity
If selective deposition is used to form gate electrodes on fin structures, then fabrication complexity is reduced, but selectivity between substrate areas must be precisely controlled
Solution Approach 1:
The patent uses the mandrel layer as an intermediary between the substrate and the gate electrode deposition process. This intermediary layer mediates the selective deposition by providing a controlled interface that directs material deposition. The mandrel layer acts as a mediator that translates the substrate pattern into selective deposition zones, reducing fabrication complexity while maintaining precise control over where material is deposited through its reactive and non-reactive area configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the manufacturability of finFET structures by enabling the formation of gate electrodes and spacer layers with improved selectivity and reduced complexity, overcoming the topography-related fabrication challenges.
Implementation Method 1
A sidewall of the mandrel layer is activated with respect to vapor deposition of a material layer upon the sidewall of the mandrel layer. A surface of the substrate is passivated with respect to vapor deposition of the material layer upon the surface of the substrate.
Data Source
AI summary
A finFET structure includes a semiconductor fin located over a substrate. A gate electrode is located traversing the semiconductor fin. The gate electrode has a spacer layer located adjoining a sidewall thereof. The spacer layer does not cover completely a sidewall of the semiconductor fin. The gate electrode and the spacer layer may be formed using a vapor deposition method that provides for selective deposition upon a sidewall of a mandrel layer but not upon an adjoining surface of the substrate so that the spacer layer does not cover completely the sidewall of the semiconductor fin. Other microelectronic structures may be fabricated using the lateral growth methodology.