Selective Epitaxial Growth for FinFET Crosshatch Defect Resolution
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Solution Overview
Problem
Current methods for forming semiconductor fins, such as replacement fin and strain relaxed buffer approaches, suffer from defects like crosshatch pattern defects and increased material costs due to thick epitaxial layers and interface issues between semiconductor fins and dielectric materials.
Innovation Solution
The method involves epitaxially growing thin semiconductor layers over a substrate with localized growth to prevent crosshatch defects and reduce interface defects, using a combination of dopants and chemical mechanical planarization to form high-quality semiconductor fins for FinFETs, which can be integrated into existing CMOS fabrication flows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If thick epitaxial films are formed over the entire wafer to provide quality epitaxial layers, then lattice mismatch is decreased and epitaxial quality is improved, but crosshatch pattern defects occur and material costs increase
Solution Approach 1:
The patent applies local quality by forming epitaxial layers only in specific regions where fins are needed, rather than over the entire wafer. This is achieved through selective epitaxial growth in trenches, which provides high-quality epitaxial layers where required while avoiding the crosshatch defects that occur with full-wafer thick epitaxial growth.
2Reliability
If replacement fin approach is used to form fins in dielectric trenches, then gate control is improved, but interface defects occur between semiconductor fins and dielectric material
Solution Approach 1:
The patent extracts the semiconductor fin formation process from the dielectric trenches and places it in semiconductor trenches instead. By removing the fins from the dielectric environment and placing them in a native semiconductor environment, the harmful interface defects between semiconductor and dielectric materials are eliminated while maintaining the gate control benefits.
3Quantity of substance
If thin epitaxial layers are grown to reduce material costs and prevent crosshatch defects, then material costs are reduced and crosshatch defects are prevented, but interface defects with dielectric layers occur
Solution Approach 1:
The patent extracts the fin formation from dielectric trenches and places it in semiconductor trenches. This eliminates the interface between semiconductor fins and dielectric materials that causes interface defects, while allowing thin epitaxial layers to be used, thus reducing material costs and preventing crosshatch defects simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces material costs and improves epitaxial film quality by growing thin semiconductor layers without sidewall interfaces with dielectric layers, minimizing defects and enhancing the performance of semiconductor devices like FinFETs.
Implementation Method 1
epitaxially growing a first semiconductor layer over the substrate
Implementation Method 2
chemical mechanical planarization to form high-quality semiconductor fins
Data Source
AI summary
A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.