FinFET Fabrication Using Selective Epitaxy and Oxide Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The drive current of FinFETs using III-V group materials needs improvement to effectively address the miniaturization challenges and physical limitations in CMOS technology, despite their high mobility and low gate leakage current.
Innovation Solution
A fabrication method for FinFETs involving the deposition of a shallow trench isolation layer, alternative oxygen-containing and insulating layers, selective epitaxial growth of a buffer and III-V group material, thermal oxidation to form an oxide-isolation layer, and the deposition of a high dielectric constant dielectric layer with a conducting gate electrode, optimizing the structure for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If III-V group material is used for FinFET fabrication, then mobility and gate leakage current are improved, but drive current is insufficient
Solution Approach 1:
The patent employs a composite structure combining III-V group material (InAs) with a buffer layer (GaAs or AlGaAs) and integrates it with silicon substrate technology. This composite approach allows leveraging the high mobility and low gate leakage of III-V materials while using the buffer layer to improve lattice matching and enhance drive current characteristics.
Solution Approach 2:
The invention applies selective epitaxial growth to create localized regions of III-V material only where needed in the fin structure, while maintaining different material compositions in different layers (buffer layer vs. channel layer). This local quality differentiation optimizes both the low gate leakage in the channel region and the drive current through proper material grading in the buffer region.
2Productivity
If FinFET miniaturization is pursued beyond 10 nm, then transistor density is improved, but physical limitations and short-channel effects worsen
Solution Approach 1:
The patent transitions from planar 2D channel structure to a three-dimensional FinFET structure with vertical fins extending from the substrate. This dimensional change increases the effective channel area for higher transistor density while maintaining electrostatic control over the channel through the wrapped gate structure, effectively mitigating short-channel effects at scaled dimensions.
Solution Approach 2:
The gate structure wraps around the fin channel in a nested configuration, with the gate electrode surrounding the channel region. This nested geometry provides superior electrostatic control compared to planar gates, enabling better short-channel effect suppression while allowing further miniaturization and increased transistor density.
3Manufacturing precision
If alternative layers of oxygen-containing dielectric layers and insulating layers are deposited, then structural control is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the dielectric structure into multiple alternative layers of oxygen-containing dielectric layers and insulating layers with different thicknesses and material compositions. Each layer serves a specific function in the selective etching process, creating the vertical stacked bowls cross-sectional shape. This segmentation enables precise structural control through selective removal of specific layers while maintaining manufacturing feasibility through standardized deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the drive current and structural control of FinFETs, addressing the limitations of III-V group material FinFETs and enabling further miniaturization beyond the 10 nm technology node.
Implementation Method 1
selective epitaxially growing a buffer layer on the substrate in the trench; selective epitaxially growing a III-V group material on the buffer layer in the trench
Implementation Method 2
thermal oxidizing the buffer layer to form an oxide-isolation layer between the substrate and the III-V group material
Data Source
AI summary
Present embodiments provide for a FinFET and fabrication method thereof. The fabrication method includes two selective etching processes to form the channel. The FinFET includes a substrate, a shallow trench isolation (STI) layer, a buffer layer, a III-V group material, an oxide-isolation layer, a high-K dielectric layer and a conductor material. The STI is formed on the substrate with a trench. The buffer layer is formed on the substrate in the trench. The III-V group material is formed on the buffer layer in vertical stacked bowl shape. The oxide-isolation layer is formed between the substrate and the III-V group material. The high-K dielectric layer is formed on the STI layer and surrounding the III-V group material. The conductor material is formed surrounding the high-K dielectric layer.