Selective Epitaxy Growth for FinFET Device Stability
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Solution Overview
Problem
FinFET devices face limitations in device width ratio due to constraints on fin number and size, making it challenging to achieve desired active area reductions for improved performance, particularly in SRAM designs where a smaller p-type FET is needed for increased stability.
Innovation Solution
An angled ion implantation process is performed on one sidewall of a fin to damage the spacer layer, which is then removed, followed by selective epitaxy growth on the exposed surface to form active regions, allowing for increased device performance without reducing the number of fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of fins is reduced to decrease the active area of the fins, then the device stability is improved, but the device width ratio is limited and performance is degraded
Solution Approach 1:
The patent applies local quality by selectively removing the spacer layer only from specific sidewalls of selected fins through angled ion implantation. This creates local variations in the fin structure where some fins have reduced active area while others maintain full active area, enabling differential device characteristics within the same circuit to achieve both stability and performance
Solution Approach 2:
The patent transitions from controlling device characteristics through the number of fins (one-dimensional approach) to controlling characteristics through the active area of individual fins by selectively removing spacer material from sidewalls (two-dimensional approach). This dimensional change allows independent optimization of device width ratio and active area without being constrained by fin count
2Manufacturing precision
If different device widths are obtained by using different numbers of fins, then the device width ratio is achieved, but the fin count flexibility is reduced and manufacturing complexity increases
Solution Approach 1:
Instead of varying the number of fins across different devices, the patent applies local quality by selectively modifying the spacer layer on sidewalls of specific fins. This allows precise control of device width ratio through localized spacer removal on selected fins while maintaining the same fin count across all devices, simplifying the manufacturing process
Solution Approach 2:
The patent employs preliminary action by forming a uniform spacer layer around all fins first, then selectively removing it from specific sidewalls through angled ion implantation. This preliminary uniform formation followed by selective modification enables precise control of device dimensions while maintaining manufacturing simplicity and consistency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively decreases the total on-resistance of FinFET devices while increasing the extension resistance, enabling improved performance without altering the fin count, thus enhancing device stability and efficiency.
Implementation Method 1
performing an angled ion implantation process at a predetermined angle on a first sidewall of a fin to cause damage to the first sidewall of the fin
Implementation Method 2
selective epitaxy growth on the exposed surface to form active regions
Data Source
AI summary
A method for forming a Fin field-effect transistor (FinFET) semiconductor structure includes performing an angled ion implantation process at a predetermined angle on a first sidewall of a fin to cause damage to the first sidewall of the fin. The damage caused to the first sidewall of the fin is removed.