FinFET Source/Drain Fabrication via Selective Oxidation

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Solution Overview

Problem

The challenge in forming complementary metal oxide semiconductor (CMOS) devices lies in the difficulty of creating smaller device components while maintaining the positive aspects of traditional FET structures, particularly in forming n-type and p-type fin field effect transistors (FinFETs) without separate masking steps and avoiding scaling issues.

Innovation Solution

The method involves forming vertical fins on a substrate, where different subsets of source/drain projections are made from distinct materials (such as silicon and silicon-germanium) that can be selectively converted to an oxide, allowing for the formation of source/drain seed mandrels and dummy posts without iterative masking and lithographic misalignments, enabling the fabrication of CMOS devices without multiple liner and organic planarization depositions and removals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If separate masking steps are used to form n-type and p-type source/drains, then manufacturing precision can be maintained, but device complexity and fabrication time increase

Engineering Contradiction:
Improvesource/drain formation precisionVSAvoidfabrication process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The source/drain projections are segmented into different materials (silicon and silicon-germanium) that can be selectively oxidized. This segmentation allows n-type and p-type source/drains to be formed through selective oxidation of different material regions, eliminating the need for separate masking steps while maintaining precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different oxidizable materials are placed at specific locations (silicon for n-type, silicon-germanium for p-type). The local material quality enables selective oxidation to occur only in desired regions, achieving precise source/drain formation without complex masking procedures.

Inventive Principle:
Principle #3Local quality

2Productivity

If device dimensions are decreased to improve integration density, then productivity increases, but manufacturing precision and reliability deteriorate

Engineering Contradiction:
Improveintegration densityVSAvoidcomponent formation precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The different oxidizable materials serve as self-aligned markers that automatically define the boundaries between n-type and p-type source/drain regions. The oxidation process itself reveals the pattern without requiring external masking, providing self-aligned precision that maintains manufacturing accuracy even as device dimensions decrease.

Inventive Principle:
Principle #25Self-service

3Manufacturing precision

If multiple liner and organic planarization depositions are used, then manufacturing precision is maintained, but loss of time and productivity decrease

Engineering Contradiction:
Improvesurface planarityVSAvoidfabrication cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent extracts and eliminates the time-consuming multiple liner and organic planarization deposition steps from the fabrication process. By using directly oxidizable materials with distinct oxidation characteristics, the process achieves the necessary surface preparation and pattern definition without these intermediate deposition and removal cycles, significantly reducing fabrication time.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for the efficient formation of CMOS devices by selectively growing n-type and p-type source/drains on vertical fins using different oxidizable materials, overcoming scaling issues and reducing the need for complex masking steps, thereby improving the fabrication process of FinFETs.

Implementation Method 1

converting all of the exposed portion of the second set of source/drain projections and at least a portion of an exposed portion of the first set of source/drain projections to an amorphous material

Methodology Applied
Scientific EffectOxidation: Oxidation

Data Source

PatentUS10083962B2Fabrication of fin field effect transistors for complementary metal oxide semiconductor devices including separate n-type and p-type source/drains using a single spacer deposition
Publication Date: 2018.09.25 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10083962B2 patent drawing
  • US10083962B2 patent drawing
  • US10083962B2 patent drawing

AI summary

A method of forming a complementary metal oxide semiconductor (CMOS) device on a substrate, including forming a plurality of vertical fins on the substrate, forming a first set of source/drain projections on the first subset of vertical fins, forming a second set of source/drain projections on the second subset of vertical fins, where the second set of source/drain projections is a different oxidizable material from the oxidizable material of the first set of source/drain projections, converting a portion of each of the second set of source/drain projections and a portion of each of the first set of source/drain projections to an oxide, removing the converted oxide portion of the first set of source/drain projections to form a source/drain seed mandrel, and removing a portion of the converted oxide portion of the second set of source/drain projections to form a dummy post.