FinFET Device Strain Engineering via Selective Oxidation
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Solution Overview
Problem
Existing FinFET devices and fabrication methods are not entirely satisfactory in achieving optimal performance due to limitations in processing and manufacturing complexity, particularly in scaling down to smaller geometries and increasing functional density.
Innovation Solution
A method for fabricating FinFET devices involves forming fin structures on a substrate with different semiconductor material layers, applying a patterned oxidation-hard-mask, and performing thermal oxidation to create semiconductor oxide features, followed by the deposition of dielectric layers and high-k/metal gate stacks to induce strain and enhance mobility in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET devices are scaled down to smaller geometries to increase functional density, then productivity and production efficiency are improved, but manufacturing complexity and processing difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential stages including forming mandrel structures, depositing first and second semiconductor material layers with different lattice constants, selective oxidation, and staged etching. This segmentation allows complex FinFET structures to be built through manageable steps, resolving the contradiction between high functional density and manufacturing complexity
Solution Approach 2:
Mandrel structures are formed in advance before the actual FinFET structures are created. These preliminary mandrels serve as templates that guide subsequent material deposition and pattern formation, enabling precise control of scaled-down geometries while simplifying the overall manufacturing process
2Reliability
If different semiconductor material layers with different lattice constants are used to induce strain, then mobility and device performance are improved, but processing and manufacturing complexity increase
Solution Approach 1:
Different semiconductor material layers with specific lattice constants are deposited in localized regions to create strain in specific areas of the channel. This local quality approach enables performance enhancement where needed while keeping other regions simpler, balancing device performance with ease of manufacture
Solution Approach 2:
The lattice constant parameter is varied by selecting different semiconductor materials (e.g., SiGe versus Si) to induce mechanical strain in the channel region. This parameter change directly improves carrier mobility and device performance without requiring fundamentally new manufacturing processes
3Reliability
If thermal oxidation is used to create semiconductor oxide features, then strain induction and mobility enhancement are improved, but manufacturing precision requirements increase
Solution Approach 1:
Patterned oxidation-hard-mask structures serve as intermediaries that control and localize the thermal oxidation process. These masks precisely define where oxide features form, enabling reliable mobility enhancement while maintaining manufacturing precision through the mediating role of the hard mask layer
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method improves device performance by efficiently inducing strain in the gate region and source/drain stressors, leading to enhanced mobility and performance in both n-type and p-type FinFET devices.
Implementation Method 1
performing thermal oxidation to create semiconductor oxide features
Implementation Method 2
deposition of dielectric layers and high-k/metal gate stacks
Data Source
AI summary
The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.