FinFET Selector Structures for Programmable Resistive Memory Cells

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Solution Overview

Problem

Conventional programmable resistive memory cells using MOS or diodes as program selectors face challenges in reducing cell size and cost, particularly in achieving thermal isolation and efficient programming in FinFET technologies.

Innovation Solution

The use of FinFET structures with diodes constructed from P+ and N+ implants in standard FinFET processes as program selectors, allowing for thermal isolation and reduced cell size without additional processing steps, and the integration of extended source/drain regions as OTP elements to minimize costs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If MOS or diodes are used as program selectors in conventional programmable resistive memory cells, then programming capability is achieved, but cell size and manufacturing cost increase

Engineering Contradiction:

Improvemanufacturing costVSAvoidcell size

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The patent merges the program selector and OTP element into a single FinFET structure. The FinFET serves dual functionality as both the program selector (controlling current flow) and the OTP element (being programmed into high resistance state), eliminating the need for separate components and reducing cell area while maintaining programming capability

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The FinFET structure is designed to perform multiple functions: it acts as a programmable resistor, a current selector, and a storage element simultaneously. This multi-functionality reduces the number of components needed in the memory cell, thereby reducing both area and manufacturing complexity

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Power

If larger program selectors are used to deliver required program current, then programming capability is improved, but cell size increases significantly

Engineering Contradiction:

Improveprogram current delivery capabilityVSAvoidcell size

Core Design Contradiction:

PowerVSArea of stationary object

Solution Approach 1:

The patent transitions from planar MOS structures to three-dimensional FinFET structures. The vertical fin structure provides increased channel width and current delivery capability without increasing the planar footprint of the device, allowing strong programming capability in a compact area

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Temperature

If additional processing steps are implemented to achieve thermal isolation, then thermal management is improved, but manufacturing complexity and cost increase

Engineering Contradiction:

Improvethermal isolationVSAvoidprocessing steps

Core Design Contradiction:

TemperatureVSDevice complexity

Solution Approach 1:

The FinFET structure provides inherent thermal isolation through its three-dimensional geometry and standard process integration. The vertical fin structure and associated process steps that are already required for FinFET fabrication naturally provide thermal management benefits without requiring additional dedicated processing steps

Inventive Principle:

Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enables the fabrication of programmable resistive devices with smaller cell sizes and reduced costs, while providing thermal isolation and efficient programming capabilities within FinFET technologies, suitable for various applications including embedded systems.

Implementation Method 1

The use of FinFET structures with diodes constructed from P+ and N+ implants in standard FinFET processes as program selectors, allowing for thermal isolation

Methodology Applied

Scientific EffectThermal isolation: Thermal Insulation

Implementation Method 2

at least one diode constructed from at least one P+ fin with at least one N well tap in FinFET technologies

Methodology Applied

Scientific EffectDiode effect: Diode

Implementation Method 3

The resistive element can be programmed by applying voltages to the first, second, and/or third supply voltage lines to thereby change the resistance into a different logic state

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Data Source

PatentUS9881970B2Programmable resistive devices using Finfet structures for selectors

Publication Date: 2018.01.30 ATTOPSEMI TECH CO LTD

AI summary

A programmable resistive memory having a plurality of programmable resistive cells. At least one of the programmable resistive cell includes a programmable resistive element and at least one selector. The selector can be built in at least one fin structure and at least one active region divided by at least one MOS gate into a first active region and a second active region. The first active region can have a first type of dopant to provide a first terminal of the selector. The second active region can have a first or a second type of dopant to provide a second terminal of the selector. The MOS gate can provide a third terminal of the selector. The first terminal of the selector can be coupled to the first terminal of the programmable resistive element. The programmable resistive element can be programmed by conducting current flowing through the selector to thereby change the resistance state.