FinFET Self-Aligned Contacts Reduce Planarization Steps
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Solution Overview
Problem
The existing transistor manufacturing processes for forming contact plugs and metal gates are complex and prone to defects, particularly in FinFET devices, due to the need for multiple planarization steps which can lead to electrical shorts and reduced yield.
Innovation Solution
The formation of self-aligned contacts using fewer planarization steps by partially filling recesses and openings with conductive material, allowing for thicker dielectric layers and improved process flexibility, and the use of multiple self-aligned dielectrics to reduce the risk of electrical shorts and enhance yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple planarization steps are performed to form contact plugs and metal gates, then the manufacturing precision is improved, but the device complexity and processing time increase
Solution Approach 1:
The patent extracts and removes unnecessary planarization steps from the conventional manufacturing process. By using self-aligned contacts that naturally form at the correct positions through the gate recess structure, the method eliminates redundant planarization operations while maintaining the required manufacturing precision for contact plug formation.
Solution Approach 2:
The patent performs preliminary actions by forming the gate recess and self-aligned contact structure before final contact plug deposition. The self-aligned contacts are prepared in advance at their precise locations through the gate recess geometry, eliminating the need for subsequent planarization steps to achieve proper alignment and positioning.
2Manufacturing precision
If multiple planarization steps are performed, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The patent removes multiple time-consuming planarization steps from the production flow. The self-aligned contact formation method achieves precise contact plug alignment through the inherent geometry of the gate recess structure, maintaining manufacturing precision while significantly reducing the number of processing steps and improving overall productivity.
3Reliability
If thicker dielectric layers are used to increase self-aligned dielectric thickness, then the reliability is improved by reducing electrical shorts, but the device complexity increases
Solution Approach 1:
The patent employs self-aligned contacts that automatically position themselves at the correct locations through the gate recess structure. This self-service mechanism eliminates the need for complex multiple planarization steps and thick dielectric layers to prevent electrical shorts, as the self-aligned geometry inherently provides proper spacing and isolation between conductive elements.
4Ease of manufacture
If conventional contact plug formation methods are used, then the manufacturing process is established, but the yield is reduced due to electrical shorts
Solution Approach 1:
The patent extracts and eliminates the source of electrical shorts by removing unnecessary planarization steps that can create defects. The self-aligned contact formation method provides inherent protection against electrical shorts through precise geometric alignment, maintaining ease of manufacture while significantly improving yield.
Solution Approach 2:
The patent performs preliminary formation of self-aligned contacts through the gate recess structure before final contact plug deposition. This preliminary action ensures proper spacing and alignment that prevents electrical shorts, thereby improving yield while maintaining process establishability.
Data Source
AI summary
A device includes a semiconductor fin protruding from a substrate, a first gate stack over the semiconductor fin and a second gate stack over the semiconductor fin, a first source/drain region in the semiconductor fin adjacent the first gate stack and a second source/drain region in the semiconductor fin adjacent the second gate stack, a first layer of a first dielectric material on the first gate stack and a second layer of the first dielectric material on the second gate stack, a first source/drain contact on the first source/drain region and adjacent the first gate stack, a first layer of a second dielectric material on a top surface of the first source/drain contact, and a second source/drain contact on the second source/drain region and adjacent the second gate stack, wherein the top surface of the second source/drain contact is free of the second dielectric material.