FinFET Self-Aligned Source Drain via Damascene Gate
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Solution Overview
Problem
FinFET devices face challenges in accurately and consistently contacting source and drain regions due to the difficulty in aligning landing pads with the gate, leading to issues with parasitic capacitance and resistance, especially as feature sizes decrease.
Innovation Solution
A method involving a damascene gate process to form self-aligned source and drain regions with a gate stack, using a dual fin hardmask structure and a dummy gate to precisely etch fins, ensuring the source and drain regions are intact and aligned with the gate stack, allowing for precise fin formation and reduced variations in fin dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If landing pads are used to contact the fins, then mechanical stability during processing is improved and device contacting scheme is simplified, but alignment precision with the gate becomes difficult to achieve
Solution Approach 1:
The source and drain regions are formed to be self-aligned with the gate structure through the sequential processing steps. The gate is formed first, then the source and drain regions are created in the spaces adjacent to the gate, automatically achieving alignment without requiring separate alignment steps for landing pads.
Solution Approach 2:
The gate structure is formed preliminarily before forming the source and drain regions. This preliminary formation of the gate establishes the reference structure that automatically defines the positions of the source and drain regions, eliminating the need for separate alignment operations.
2Reliability
If landing pads are used to contact the fins, then external resistance is reduced, but alignment precision with the gate becomes difficult to achieve
Solution Approach 1:
The source and drain regions are formed to be self-aligned with the gate structure through the sequential processing steps. The gate is formed first, then the source and drain regions are created in the spaces adjacent to the gate, automatically achieving alignment without requiring separate alignment steps for landing pads.
Solution Approach 2:
The gate structure is formed preliminarily before forming the source and drain regions. This preliminary formation of the gate establishes the reference structure that automatically defines the positions of the source and drain regions, eliminating the need for separate alignment operations.
3Adaptability or versatility
If individual fin contacting is implemented without landing pads, then alignment flexibility is improved, but contacting difficulty increases due to mismatches between minimum fin pitch and minimum pitch for contact vias
Solution Approach 1:
The gate structure serves multiple functions: it acts as the control electrode for the transistor and simultaneously serves as the alignment reference for forming the source and drain regions. This multi-functionality eliminates the need for separate alignment operations and accommodates various pitch requirements.
Solution Approach 2:
The source and drain regions are formed to be self-aligned with the gate structure through the sequential processing steps. The gate is formed first, then the source and drain regions are created in the spaces adjacent to the gate, automatically achieving alignment without requiring separate alignment steps for landing pads.
4Productivity
If feature sizes are reduced to achieve higher integration density, then device scaling is improved, but alignment precision for contacting source and drain becomes more difficult
Solution Approach 1:
The source and drain regions are formed to be self-aligned with the gate structure through the sequential processing steps. The gate is formed first, then the source and drain regions are created in the spaces adjacent to the gate, automatically achieving alignment without requiring separate alignment steps for landing pads.
Solution Approach 2:
The gate structure is formed preliminarily before forming the source and drain regions. This preliminary formation of the gate establishes the reference structure that automatically defines the positions of the source and drain regions, eliminating the need for separate alignment operations.
Data Source
AI summary
Improved fin field effect transistor (FinFET) devices and methods for the fabrication thereof are provided. In one aspect, a field effect transistor device is provided. The field effect transistor device includes a source region; a drain region; a plurality of fins connecting the source region and the drain region, the fins having a pitch of between about 40 nanometers and about 200 nanometers and each fin having a width of between about ten nanometers and about 40 nanometers; and a gate stack over at least a portion of the fins, wherein the source region and the drain region are self-aligned with the gate stack.