FinFET Self-Aligning Mask Process for Via Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating FinFETs due to electrical shorts/leakage between gate electrodes and source/drain contacts, particularly during the formation of vias, which can lead to misalignment issues.
Innovation Solution
A cost-effective process flow is implemented using self-aligning masks over both the gate electrode and source/drain contacts, ensuring that vias do not electrically short the gate electrode to the source/drain contacts, even when misaligned, by forming a mask over both and using a gate-last or gate-first process to align vias correctly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vias are formed to gate electrode and source/drain contacts without self-aligning masks, then via formation process is simpler, but electrical shorts/leakage between gate electrode and source/drain contacts occur due to misalignment
Solution Approach 1:
The patent combines the gate electrode and source/drain contacts into a single common reference plane. By forming both structures to the same depth and using a shared dielectric layer, the via formation process uses a single alignment reference, eliminating misalignment issues between separate gate and contact vias while maintaining electrical isolation through the common dielectric barrier.
Solution Approach 2:
The patent performs preliminary actions by pre-forming the gate electrode and source/drain contacts to the same depth and establishing the common dielectric layer before via formation. This preliminary structuring creates self-aligning features that guide subsequent via formation, ensuring proper alignment without requiring complex masking processes.
2Reliability
If gate electrode layout is extended to prevent misalignment, then via placement safety is improved, but manufacturing efficiency decreases due to larger device footprint
Solution Approach 1:
The patent performs preliminary alignment by forming the gate electrode and source/drain contacts to the same depth and using the same dielectric layer as a reference plane. This preliminary structuring creates self-aligning features that guide subsequent via formation, ensuring proper alignment without requiring extended gate layouts, thereby maintaining compact device footprints and high manufacturing efficiency.
3Manufacturing precision
If self-aligning masks are formed over gate electrode and source/drain contacts, then via alignment precision is improved, but manufacturing process complexity increases
Solution Approach 1:
The patent merges the alignment references for gate and contact vias by forming both structures to the same depth and using a common dielectric layer. This unified reference system provides self-alignment during via formation, achieving high manufacturing precision without requiring separate complex masking processes for gate and contact vias.
Solution Approach 2:
The patent performs preliminary structuring by forming the gate electrode and source/drain contacts to the same depth and establishing the common dielectric layer before via formation. This creates inherent self-aligning features that simplify the via formation process, achieving high precision while reducing overall process complexity compared to separate masking approaches.
Data Source
AI summary
An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.