FinFET Gate Separation Plug for Void-Free Metal Gate Filling
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Solution Overview
Problem
Existing semiconductor fabrication technologies face challenges in efficiently forming three-dimensional fin structures for Fin FET devices, particularly in ensuring complete filling of metal gate materials without voids and achieving smaller device dimensions.
Innovation Solution
The method involves forming a separation plug made of insulating material to separate metal gate structures, eliminating the need for gate dielectric and underlying metal layers on the separation plug's side surface, allowing for larger gate openings and complete filling of metal gate materials without voids, thereby enabling smaller device dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional gate dielectric and underlying metal layers are used in metal gate structures, then gate insulation is achieved, but device dimensions cannot be further reduced due to space constraints and void formation
Solution Approach 1:
The patent removes the gate dielectric layer and underlying metal layers from the gate structure, retaining only the metal gate electrode. This extraction eliminates the space occupied by insulating layers, enabling smaller device dimensions while preventing void formation in the metal gate material during fabrication
Solution Approach 2:
The gate structure is segmented into separate functional components: the metal gate electrode is formed independently without requiring continuous gate dielectric or underlying metal layers. This segmentation allows optimized spacing and positioning, improving manufacturing precision
2Productivity
If smaller device dimensions are pursued, then device density increases, but complete filling of metal gate materials without voids becomes more difficult
Solution Approach 1:
The metal gate electrode is formed using preliminary deposition and patterning steps that ensure complete material filling before subsequent processing. The gate structure is prepared in advance with appropriate geometry and material distribution to prevent void formation during later fabrication stages
Solution Approach 2:
The patent modifies the physical and chemical parameters of the metal gate electrode formation process, including deposition conditions, material composition, and structural geometry, to optimize filling behavior at smaller dimensions and eliminate voids
Data Source
AI summary
A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. The first gate electrode layer is in contact with a side wall of the separation plug.