FinFET Transistor Fin Height Optimization for SEU Mitigation
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Solution Overview
Problem
FinFET transistors in front end circuits, such as SRAM structures, are susceptible to single event upsets (SEU) due to high energy particle strikes, leading to increased Soft Error Rate (SER), which is challenging to address without increasing die area and cost.
Innovation Solution
Increasing the fin height of FinFET transistors beyond the optimal height for optimal speed reduces the recovery time and enhances the restoring current, thereby decreasing the SEU error rate with negligible impact on die area, making the transistors more resistant to high energy particle strikes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fin height of FinFET transistors is increased beyond the optimal height, then the SEU error rate is reduced and reliability is improved, but the transistor speed deteriorates
Solution Approach 1:
The patent applies parameter changes by intentionally increasing the fin height parameter beyond its optimal value for speed. This parameter modification (height > HOPT) transforms the transistor's electrical characteristics to enhance restoring current and reduce SEU susceptibility, accepting a trade-off in speed performance. The specific parameter change is the fin height dimension, which is deliberately oversized to improve reliability metrics.
2Reliability
If the fin height of FinFET transistors is increased to reduce SEU error rate, then the recovering time is reduced, but the die area increases
Solution Approach 1:
The patent modifies the fin height parameter to achieve SEU mitigation while controlling die area impact. By optimizing the extent of height increase beyond HOPT, the design balances reliability improvement against area overhead. The parameter change approach allows quantitative control over the trade-off between SEU error rate reduction and die area increase.
Data Source
AI summary
Front end circuits that include a FinFET transistor are described herein. In one example, the front end circuit has a FinFET transistor that includes a channel region wrapped by a metal gate, the channel region connecting a source and drain fins. At least one of the source and drain fins have a height (HTOT) and a width W. The height (HTOT) is greater than an optimal height (HOPT), wherein the height HOPT is a height that would optimize speed of a FinFET transistor having the width W.