FinFET Shared Gate Structure Bump Reduction
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Solution Overview
Problem
The manufacturing of FinFET devices with shared gate structures faces challenges such as the formation of a large 'bump' during the CMP process, which complicates achieving a planar surface, and high aspect ratios that make it difficult to develop accurate photoresist masks, leading to issues like scumming and overconsumption of photoresist masks during etching.
Innovation Solution
A method involving forming a shared sacrificial gate structure with a single process operation to create sidewall spacers around the entire perimeter, followed by etching and epi deposition processes that reduce the height of the bump and improve planarity, using silicon nitride and dioxide materials to minimize cap layer consumption and photoresist mask issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared sacrificial gate structure is formed with a single process operation to create sidewall spacers around the entire perimeter, then the manufacturing complexity is reduced and productivity is improved, but the aspect ratio becomes very high which makes it difficult to form accurate photoresist masks
Solution Approach 1:
The patent divides the fin structure into multiple segments by forming recesses in the fins. This segmentation reduces the effective height that the photoresist mask needs to cover, making mask formation more accurate. The fins are recessed to different depths creating multiple levels, which breaks the continuous high aspect ratio into manageable segments.
Solution Approach 2:
The patent introduces a vertical dimension variation by forming recesses at different depths in the fins. Instead of a uniform flat surface, the fin tops are positioned at different elevations, creating a stepped structure. This dimensional change reduces the aspect ratio that the photoresist mask must accommodate while maintaining the shared gate structure benefit.
2Manufacturing precision
If the bump height is reduced to 3-7 nm to facilitate CMP processing, then the manufacturing precision is improved, but additional etching and epi deposition processes are required increasing the number of process steps
Solution Approach 1:
The patent performs preliminary recessing of the fins before forming the sacrificial gate and spacers. By pre-positioning the fin surfaces at appropriate elevations through selective etching, the subsequent CMP process requires less material removal and achieves better planarity. The epi deposition is used to adjust heights preliminarily before final CMP processing.
Solution Approach 2:
The patent changes the physical and chemical parameters of the fin structures by performing selective etching to create recesses at different depths. The etch depth, etch rate, and etch selectivity are adjusted to achieve the desired bump height reduction. Epi deposition parameters (temperature, pressure, material composition) are controlled to achieve precise height adjustments.
3Loss of substance
If silicon nitride and dioxide materials are used to minimize cap layer consumption, then material efficiency is improved, but the etching selectivity requirements become more stringent
Solution Approach 1:
The patent applies different materials (silicon nitride and silicon dioxide) to different local regions of the structure. The cap layer is formed with specific material composition and thickness variations at different locations. The etching process uses selective chemistry that targets specific material combinations, requiring precise control of etch selectivity between nitride, oxide, and underlying layers at each local position.
Solution Approach 2:
The patent uses composite material structures combining silicon nitride and silicon dioxide layers in specific configurations. These composite structures provide both the protective function (minimizing cap layer consumption) and the etching selectivity needed for precise processing. The multi-layer composite design allows differential etching rates that protect underlying structures while removing sacrificial materials.
Data Source
AI summary
In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.