FinFET Shielding Layer for Contact Hole Etching Control
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Solution Overview
Problem
Existing FinFET devices face challenges in the contact hole defining process, particularly with scaling down, where conventional cap layers provide inadequate protection to adjacent spacers and dielectric materials, leading to over-etching and misalignment issues that affect device reliability and leakage.
Innovation Solution
The introduction of a shielding layer formed on the surfaces of the gate stacks, spacers, and dielectric layers, with a second dielectric layer that has different etching rates, allowing for controlled multi-step etching to define contact holes without damaging adjacent structures, and a connector formed through these layers to improve etching profiles and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional cap layers are used in the contact hole defining process, then the process is simple, but the protection to adjacent spacers and dielectric materials is inadequate, leading to over-etching and misalignment issues
Solution Approach 1:
The patent divides the protective layer into multiple segments: a first dielectric layer formed aside the gate stack, and a shielding layer formed on top surfaces. This segmentation allows each layer to perform its specific protective function independently, preventing over-etching of adjacent structures while maintaining process control.
Solution Approach 2:
The patent performs preliminary protective actions by forming the first dielectric layer and shielding layer before the contact hole etching process. These layers are prepared in advance to protect adjacent spacers and dielectric materials from damage during subsequent etching operations, preventing misalignment and over-etching issues.
2Productivity
If scaling down is continued to increase functional density, then production efficiency increases and costs decrease, but the complexity of processing and manufacturing increases
Solution Approach 1:
The patent applies local quality by forming the shielding layer specifically on top surfaces where protection is needed, rather than uniformly across the entire structure. The first dielectric layer is formed aside the gate stack in specific regions. This localized approach provides necessary protection at scaled dimensions without adding excessive complexity to the overall manufacturing process.
3Manufacturing precision
If a shielding layer with different etching rates is introduced, then protection of adjacent structures is improved and over-etching is reduced, but the number of process steps increases
Solution Approach 1:
The patent utilizes parameter changes by selecting materials for the first dielectric layer and shielding layer with different etching rates. This allows the etching process to selectively remove material at different speeds, enabling precise contact hole formation while protecting adjacent structures. The different etching rates provide inherent process control without requiring additional alignment steps.
Data Source
AI summary
Semiconductor devices, FinFET devices and methods of forming the same are provided. In accordance with some embodiments, a semiconductor device includes a substrate, a first gate stack, a spacer, a first dielectric layer, a shielding layer and a connector. The first gate stack is over the substrate. The spacer is disposed on and contacted to at least one sidewall of the first gate stack. The first dielectric layer is aside the spacer. The shielding layer covers a top surface of the spacer and a top surface of the first dielectric layer. The connector contacts a portion of a top surface of the first gate stack.