FinFET Source/Drain Extension Doping With Si:As Diffusion Control
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Solution Overview
Problem
In FinFETs, the diffusion of phosphorous atoms from source/drain extensions into the channel region is a concern, especially in smaller devices, leading to increased contact resistance and reduced transistor performance.
Innovation Solution
The method involves forming an arsenic doped silicon layer on the side wall and bottom of a semiconductor fin using selective epitaxial deposition, and then forming a source/drain region on this layer, which controls the doping of the source/drain extension region and reduces dopant diffusion into the channel.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If higher concentrations of phosphorous atoms are used in source/drain extensions, then contact resistance is reduced, but dopant diffusion into the channel region is greatly increased
Solution Approach 1:
An undoped semiconductor layer is introduced as an intermediary barrier between the heavily doped source/drain extension and the channel region. This intermediate layer prevents phosphorous atoms from diffusing into the channel while allowing the source/drain extension to maintain high dopant concentration for low contact resistance.
Solution Approach 2:
The source/drain structure is segmented into multiple regions: a heavily doped source/drain extension region for low contact resistance, an undoped intermediate layer to prevent diffusion, and a lightly doped channel region. This segmentation allows each region to be optimized independently.
2Area of stationary object
If FinFET dimensions are reduced to minimize transistor size, then footprint is reduced, but phosphorous diffusion from source/drain extension into channel is greatly increased
Solution Approach 1:
The undoped semiconductor layer serves as a diffusion barrier that becomes increasingly critical as FinFET dimensions are reduced. In smaller devices, the relative impact of dopant diffusion is magnified, making the intermediary layer essential for maintaining channel integrity while preserving the compact footprint.
3Speed
If gate width is increased to improve drive current and speed, then transistor performance is improved, but transistor size increases
Solution Approach 1:
The invention transitions from planar transistors to FinFETs, utilizing the third dimension (vertical fin structure) to increase the effective channel area and drive current without proportionally increasing the planar footprint. The fin-shaped channel region provides greater surface area for current flow while maintaining a compact device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces contact resistance while minimizing dopant diffusion into the channel, thereby enhancing the performance and reliability of FinFET transistors, especially in smaller geometries.
Implementation Method 1
forming an arsenic doped silicon layer on the side wall and the bottom by a selective epitaxial deposition process
Implementation Method 2
strong diffusion of phosphorous atoms from heavily phosphorus doped silicon (Si:P) regions into the channel is a concern
Data Source
AI summary
Embodiments of the present disclosure relate to methods for forming a source/drain extension. In one embodiment, a method for forming an nMOS device includes forming a gate electrode and a gate spacer over a first portion of a semiconductor fin, removing a second portion of the semiconductor fin to expose a side wall and a bottom, forming a silicon arsenide (Si:As) layer on the side wall and the bottom, and forming a source/drain region on the Si:As layer. During the deposition of the Si:As layer and the formation of the source/drain region, the arsenic dopant diffuses from the Si:As layer into a third portion of the semiconductor fin located below the gate spacer, and the third portion becomes a doped source/drain extension region. By utilizing the Si:As layer, the doping of the source/drain extension region is controlled, leading to reduced contact resistance while reducing dopants diffusing into the channel region.