FinFET Symmetrical Morphology via Dual Sidewall Spacer Etching
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Solution Overview
Problem
Conventional methods for forming fin field effect transistors (FinFETs) struggle to achieve the required small fin width necessary for advancing semiconductor technology, leading to asymmetrical fin morphology and compromised electrical properties due to differences in etching conditions on both sides of the fin top.
Innovation Solution
The method involves forming first and second sidewall spacers on a semiconductor substrate, adjusting their widths to be equal by etching, and using these spacers as an etch mask to form fins with a symmetrical morphology, ensuring consistent etching conditions and improved electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional mask etching is used to form fins, then the fin width can be reduced to meet Moore's Law requirements, but the fin morphology becomes asymmetrical and electrical properties deteriorate
Solution Approach 1:
The etch mask is segmented into multiple components: a sacrificial layer and two separate sidewall spacers (first and second sidewall spacers). This segmentation allows independent formation and adjustment of each component, enabling precise control over fin width and symmetrical morphology. The first sidewall spacer is formed on one side of the sacrificial layer, and the second sidewall spacer is formed on the other side, with their widths adjusted to be equal to ensure symmetry.
Solution Approach 2:
The sacrificial layer acts as an intermediary structure that facilitates the formation of symmetrical sidewall spacers. By forming sidewall spacers on both sides of the sacrificial layer and then removing the sacrificial layer, the process ensures that the remaining sidewall spacers define the fin width symmetrically. This intermediary approach solves the asymmetry problem inherent in conventional single-mask etching methods.
2Productivity
If fin width is reduced to increase device density, then chip density increases, but gate control ability decreases and short-channel effects increase
Solution Approach 1:
The invention transitions from conventional planar etching to a three-dimensional sidewall spacer-based approach. By forming sidewall spacers vertically on both sides of the sacrificial layer and using them as etch masks, the process achieves precise width control in the lateral dimension while maintaining symmetrical morphology. This dimensional approach enables reduced fin width for higher density while preserving gate control through symmetrical fin structures that minimize short-channel effects.
Data Source
AI summary
Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology.