FinFET Source/Drain SiGe Buffer Structure for Lower Resistance
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Solution Overview
Problem
The challenge in IC devices is to enhance the performance and reliability of field-effect transistors (FETs) with fin-type active regions while ensuring high operating speed and accuracy, particularly in the context of increased integration density and reduced device sizes.
Innovation Solution
The IC device incorporates a source/drain region with a stacked structure of buffer layers having varying germanium (Ge) concentrations, including a first buffer layer and a second buffer layer that conformally covers the first buffer layer, with a thickness ratio of 0.9 to 1.1, to reduce resistance and improve electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the integration density of IC devices is increased and device sizes are reduced, then the miniaturization and integration capability are improved, but the performance and reliability of field-effect transistors deteriorate
Solution Approach 1:
The source/drain region is divided into multiple layers with different Ge concentrations (first buffer layer with lower Ge concentration, second buffer layer with intermediate Ge concentration, and main body layer with higher Ge concentration). This graded structure provides locally optimized properties: lower Ge concentration near the fin-type active region reduces misfit dislocation, while higher Ge concentration in the main body provides stress for hole mobility enhancement, thus maintaining FET reliability during miniaturization
Solution Approach 2:
The source/drain region employs a composite multi-layer structure combining SiGe layers with different Ge concentrations. This composite approach allows simultaneous achievement of lattice matching (lower Ge concentration layers) and stress-induced mobility enhancement (higher Ge concentration layers), resolving the reliability deterioration issue that arises from simple material uniformity in scaled-down devices
2Reliability
If the Ge concentration in the source/drain region is increased to improve hole mobility, then the electrical performance is improved, but the misfit dislocation with the channel region increases
Solution Approach 1:
The Ge concentration parameter is gradually changed across the source/drain region thickness. The first buffer layer has lower Ge concentration (e.g., 5-20%) to reduce misfit dislocation, the second buffer layer has intermediate Ge concentration (e.g., 20-40%) as a transition, and the main body layer has higher Ge concentration (e.g., 40-70%) to provide stress for hole mobility. This parameter gradient resolves the contradiction between electrical performance and misfit dislocation
Solution Approach 2:
The first and second buffer layers are formed as preliminary structures before the main body layer. These buffer layers pre-establish a graded Ge concentration profile that prepares the lattice structure for subsequent high Ge concentration material, preventing sudden lattice mismatch and reducing misfit dislocation while enabling the main body layer to provide necessary stress for electrical performance
3Ease of manufacture
If a simple source/drain structure is used to reduce manufacturing complexity, then the ease of manufacture is improved, but the ability to reduce resistance and improve electrical performance deteriorates
Solution Approach 1:
Rather than using a single uniform source/drain layer, the invention changes the Ge concentration parameter across multiple layers. This parameter variation enables resistance reduction through stress-induced hole mobility enhancement while maintaining manufacturing feasibility through sequential epitaxial growth processes that can control Ge concentration profiles
4Reliability
If high Ge concentration is used throughout the source/drain region to maximize hole mobility, then the electrical performance is improved, but the lattice mismatch with the channel region worsens
Solution Approach 1:
Different regions of the source/drain structure have different Ge concentrations optimized for their specific functions. The buffer layers have lower Ge concentration for lattice matching and structural stability, while the main body layer has higher Ge concentration for stress-induced hole mobility. This local quality differentiation resolves the contradiction between hole mobility and lattice matching stability
Data Source
AI summary
An integrated circuit (IC) device includes a fin-type active region, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region, a source/drain region that is adjacent to the gate line on the fin-type active region and has a sidewall facing the channel region, wherein the source/drain region includes a first buffer layer, a second buffer layer, and a main body layer, which are sequentially stacked in a direction away from the fin-type active region, each include a Si1-xGex layer (x≠0) doped with a p-type dopant, and have different Ge concentrations, and the second buffer layer conformally covers a surface of the first buffer layer that faces the main body layer. A thickness ratio of the side buffer portion to the bottom buffer portion is in a range of about 0.9 to about 1.1.