FinFET Channel Defect Reduction via SiGe Composition Gradients
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Solution Overview
Problem
The integration of alternative semiconductor materials with silicon substrates in FinFET devices is hindered by lattice constant mismatches, leading to defects and manufacturing challenges, particularly in forming defect-free alternative fin materials with unstrained crystalline planes.
Innovation Solution
The method involves forming doped fins with a doped region extending vertically and laterally, followed by the growth of silicon/germanium or other alternative semiconductor materials around these fins, and the creation of a gate structure to enhance the fin's properties, using techniques such as ion implantation and epitaxial growth to minimize defects and optimize material properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If alternative semiconductor materials are integrated with silicon substrates in FinFET devices, then device performance and switching speed are improved, but lattice constant mismatches cause defects and manufacturing challenges
Solution Approach 1:
The alternative semiconductor material layer is segmented into multiple thin sub-layers with gradually changing composition (e.g., SiGe with increasing Ge content from bottom to top). This gradient structure allows progressive adaptation to the lattice constant mismatch between silicon substrate and high-Ge-content material, reducing dislocation defects while maintaining high switching speed performance.
Solution Approach 2:
The lattice constant mismatch parameter is dynamically managed by varying the semiconductor material composition throughout the layer thickness. By changing the Ge content gradient, the effective lattice constant transitions smoothly from matching silicon at the interface to matching the desired high-performance material at the top surface, eliminating defects while preserving speed improvements.
2Speed
If the channel length of FETs is decreased to improve operating speed and density, then switching speed increases, but short channel effects degrade the active switch characteristic
Solution Approach 1:
The invention transitions from planar 2D channel structure to three-dimensional FinFET structure with vertical fins extending from the substrate. This adds a vertical dimension to the channel, increasing the effective channel width-to-footprint ratio and enhancing gate control over the channel, which suppresses short channel effects while maintaining short horizontal channel length for high switching speed.
Solution Approach 2:
The channel region utilizes composite material structure combining silicon substrate with alternative semiconductor materials (e.g., SiGe, III-V materials) in the fin regions. This composite approach leverages the high mobility properties of alternative materials in the vertical channel while maintaining compatibility with silicon processing, achieving both high speed and reliable switching characteristics despite short channel dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces defects and enhances the performance of FinFET devices by forming substantially defect-free alternative fin materials with improved crystalline quality, leading to increased reliability and performance, particularly in reducing short channel effects and leakage currents.
Implementation Method 1
forming a doped fin for the device, wherein the doped fin includes a doped region
Implementation Method 2
forming a layer of silicon/germanium (SixGe1-x) around at least a portion of the doped fin
Data Source
AI summary
Disclosed are methods and devices that involve formation of alternating layers of different semiconductor materials in the channel region of FinFET devices. The methods and devices disclosed herein involve forming a doped silicon substrate fin and thereafter forming a layer of silicon/germanium around the substrate fin. The methods and devices also include forming a gate structure around the layer of silicon/germanium using gate first or gate last techniques.