FinFET Source/Drain SiGe Profile for Lower Channel Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in reducing channel resistance, source/drain resistance, and improving device performance due to increased complexity in forming efficient source/drain regions with high germanium and dopant concentrations while maintaining reduced volume and waviness.
Innovation Solution
The process involves epitaxially growing multiple source/drain layers with varying germanium concentrations and dopant levels at specific temperatures and pressures, followed by conformal deposition of additional layers to form source/drain regions with increased waviness and reduced volume, enhancing contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature size is reduced to increase integration density, then more components can be integrated into a given area, but channel resistance, source/drain resistance, and device performance deteriorate
Solution Approach 1:
The patent applies local quality by creating source/drain regions with non-uniform germanium concentration distribution. The germanium concentration is highest at the interface with the channel and decreases towards the surface, providing localized high carrier concentration exactly where needed to reduce channel resistance, while maintaining lower concentration elsewhere to control overall doping levels and prevent unwanted effects.
Solution Approach 2:
The patent utilizes parameter changes by varying germanium concentration through controlled diffusion processes. By adjusting diffusion temperature, time, and source configuration, the patent achieves different germanium concentration profiles that optimize both resistance reduction and device performance. The germanium concentration is changed as a continuous parameter rather than a fixed value.
2Reliability
If high germanium concentration is used to reduce channel resistance, then device performance improves, but source/drain region volume increases and waviness increases
Solution Approach 1:
The patent concentrates germanium atoms locally at the source/drain-channel interface rather than distributing them uniformly throughout the source/drain region. This localized concentration achieves high carrier density for low resistance without requiring increased overall source/drain volume. The germanium concentration is spatially differentiated to provide maximum benefit with minimum material.
3Reliability
If dopant concentration is increased to reduce source/drain resistance, then electrical conductivity improves, but manufacturing complexity increases
Solution Approach 1:
The patent changes the doping parameter from traditional uniform phosphorus or boron doping to germanium diffusion with spatially varying concentration. This single parameter change (using germanium instead of traditional dopants) simultaneously achieves low resistance and simplified manufacturing by eliminating the need for multiple sequential doping steps and complex dopant profile engineering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced channel resistance, source/drain resistance, improved device performance, decreased gate-to-drain capacitance, and increased device speed.
Implementation Method 1
epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C. and a pressure of 5 Torr to 50 Torr
Implementation Method 2
conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C. and a pressure of greater than 20 Torr
Data Source
AI summary
A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.