FinFET IC Structure With SiGe PMOS for SRAM Write Margin

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Traditional FinFET fabrication methods face challenges in optimizing embedded SRAM manufacturing, particularly concerning SRAM cell write margin and logic circuit speeds.

Innovation Solution

The implementation of FinFET logic circuits and SRAM cells that enhance SRAM cell write margin without compromising logic circuit speeds, achieved through specific design and material choices for the FinFET devices, such as using SiGe for PMOSFETs and silicon for NMOSFETs, and optimizing fin widths and source/drain regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional FinFET fabrication methods are used, then manufacturing process is simple, but SRAM cell write margin is insufficient and logic circuit speeds are compromised

Engineering Contradiction:

ImproveSRAM cell write marginVSAvoidFinFET fabrication process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different materials to different transistor types within the same FinFET structure. Specifically, SiGe is used for PMOSFET fins while silicon is used for NMOSFET fins, creating local material quality variations that optimize SRAM cell write margin without requiring complete process redesign

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The invention employs composite material structures by combining SiGe and silicon in the same integrated circuit. The SiGe material provides enhanced hole mobility for PMOSFETs, while silicon maintains electron mobility for NMOSFETs, achieving improved SRAM performance through material composition optimization

Inventive Principle:

Principle #40Composite materials

2Reliability

If SiGe is used for PMOSFETs and silicon for NMOSFETs, then SRAM cell write margin is improved, but manufacturing process complexity increases

Engineering Contradiction:

ImproveSRAM cell write marginVSAvoidFinFET fabrication ease

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

The fabrication process is segmented into distinct stages: forming SiGe fins for PMOSFETs in first wells, forming silicon fins for NMOSFETs in second wells, then forming a common gate structure over both. This segmentation allows different materials to be processed separately before integration, managing manufacturing complexity

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent merges the gate formation process to be common for both SiGe-based PMOSFETs and silicon-based NMOSFETs. The gate electrode and gate dielectric are formed simultaneously over both fin types, combining previously separate processes into a unified step that reduces overall manufacturing complexity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS20250089319A1Integrated circuit structure

Publication Date: 2025.03.13 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit (IC) structure includes first and second semiconductor channel patterns extending over a substrate. From a plan view, the second semiconductor channel pattern has a longitudinal axis aligned with a longitudinal axis of the first semiconductor channel pattern, the first semiconductor channel pattern has a first longitudinal side and a second longitudinal side separated from the first longitudinal side by a first distance, and the second channel pattern has a third longitudinal side and a fourth longitudinal side separated from the third longitudinal side by a second distance less than the first distance.