FinFET Gate And Contact Layout For SiGe Strain Retention

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Solution Overview

Problem

Traditional FinFET fabrication methods face challenges in optimizing isolation structures, leading to strain loss in SiGe fins and complicating scaling down capabilities due to the need for additional gate cut processes.

Innovation Solution

The proposed solution involves forming dielectric dummy gates between abutted circuit cells without the additional gate cut process, using self-aligned processes like double-patterning or multi-patterning to create patterns with smaller pitches, and employing a sacrificial layer to pattern fins and gate structures, thereby reducing strain loss and simplifying the fabrication process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional FinFET fabrication methods are used with isolation structures, then device isolation is achieved, but strain loss occurs in SiGe fins

Engineering Contradiction:
Improvestrain maintenance in SiGe finsVSAvoidfabrication process complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent removes the isolation structure from between abutted circuit cells, extracting the source of strain loss. By eliminating the isolation structure that caused strain relaxation in SiGe fins, the invention maintains strain in the fin regions while still achieving adequate isolation through alternative means such as dielectric layers formed after fin patterning.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent performs fin patterning and strain layer formation before forming dielectric isolation layers. By establishing the fin structures and strain layers first, the invention ensures that strain is maintained in the SiGe fins before any isolation structures are introduced, preventing strain loss that would occur with traditional isolation-first approaches.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If additional gate cut processes are implemented, then circuit cell isolation is improved, but manufacturing complexity increases

Engineering Contradiction:
Improvecircuit cell isolationVSAvoidfabrication process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines the isolation function with the gate dielectric layer formation process. Instead of using separate gate cut processes to isolate circuit cells, the invention forms a continuous gate dielectric layer that provides isolation between abutted cells while maintaining gate functionality, thereby merging isolation and gate formation into a single integrated process.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The gate dielectric layer serves multiple functions simultaneously: it acts as the gate insulator for transistor operation and provides isolation between abutted circuit cells. This multi-functional approach eliminates the need for dedicated isolation structures or gate cut processes, reducing fabrication complexity while maintaining both gate functionality and cell isolation.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Manufacturing precision

If self-aligned patterning processes are used, then pitch reduction is achieved, but manufacturing complexity increases

Engineering Contradiction:
Improvepattern pitchVSAvoidpatterning process steps
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent employs multi-patterning techniques where patterns are formed in nested stages. First, mandrel structures are formed and patterned; then spacer layers are deposited conformally on the mandrels; finally, the mandrels are removed and the spacers form the final pattern. This nested approach enables pitch reduction by effectively doubling or quadrupling the pattern density while using standard lithography tools.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent uses spacer layers as intermediary structures to transfer patterns from mandrels to final features. The spacers act as a mediating element that allows pattern multiplication without requiring direct lithographic patterning at the final pitch, enabling precise pattern formation through self-aligned deposition and etching processes.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11996360B2Semiconductor device and manufacturing method thereof
Publication Date: 2024.05.28 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11996360B2 patent drawing
  • US11996360B2 patent drawing
  • US11996360B2 patent drawing

AI summary

A semiconductor structure includes a channel region of a transistor in a semiconductor fin, source and drain regions of the transistor on the semiconductor fin and at opposite sides of the channel region, a gate of the transistor over the channel region, and a first metal structure. The first metal structure is disposed over a first one of the source and drain regions. The first metal structure includes a first portion lower than a top surface of the gate, a second portion higher than the top surface of the gate, and a third portion over the second portion, wherein the second portion is narrower than the first portion, and the third portion is wider than the second portion.