FinFET Single Diffusion Break Formation via CMP
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Solution Overview
Problem
The existing method for forming single diffusion breaks in FinFET fabrication is challenging due to difficulties in etching, increased risk of charge leakage, deteriorated trench filling performance, contact issues between metal gates and layers, and asymmetric epitaxial surfaces, which affect the performance of FinFET devices.
Innovation Solution
A method involving the formation of strip fins and dummy gates on a substrate, followed by etching to create a single diffusion region trench, depositing a filling material, and performing chemical mechanical planarization to form a single diffusion break, allowing for the replacement of dummy gates with metal gates without expanding the critical dimension, thereby improving contact performance and reducing asymmetry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If single diffusion breaks are formed before fins are finished to increase device density, then the occupied area of gate arrays is reduced, but the etching process becomes difficult and charge leakage risk increases
Solution Approach 1:
The patent forms single diffusion breaks after fins are completed rather than before, reversing the conventional sequence. This preliminary action of finishing fins first allows for better etching control and reduced charge leakage, while still achieving the goal of high device density through subsequent optimized processing steps
2Productivity
If single diffusion breaks are formed before fins are finished, then device density increases, but trench filling performance deteriorates due to large aspect ratio
Solution Approach 1:
The patent delays the formation of single diffusion breaks until after fins are completed, allowing the fin structure to be fully established first. This sequence change enables better trench filling performance by reducing the aspect ratio during the critical fill process, while maintaining high device density through subsequent processing
3Reliability
If a large dummy gate is used to avoid high leakage current, then leakage current is reduced, but contact performance between metal gate and metal layer deteriorates
Solution Approach 1:
The patent applies different dummy gate sizes to different regions: larger dummy gates are used in specific areas where leakage current suppression is critical, while smaller dummy gates are used in other areas where contact performance is prioritized. This localized approach allows optimization of both leakage suppression and contact performance in their respective regions
4Productivity
If single diffusion breaks are formed before fins are finished, then device density increases, but asymmetric epitaxial surface is created
Solution Approach 1:
The patent completes fin formation and establishes symmetric epitaxial surfaces before forming single diffusion breaks. This sequencing ensures that the epitaxial growth occurs on symmetric structures, maintaining surface symmetry and compositional stability, while device density is subsequently increased through the single diffusion break formation process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the contact performance between metal gates and layers, improves trench filling, and maintains a symmetrical epitaxial surface, leading to better device performance and higher yield by avoiding the issues associated with traditional single diffusion break formation.
Implementation Method 1
performing chemical mechanical planarization (CMP) on the interlayer dielectric layer to expose a top of one of the plurality of dummy gates
Data Source
AI summary
The present application provides a method for manufacturing a fin field-effect transistor, comprising steps of: forming a plurality of strip fins and dummy gates on a substrate, wherein side walls are formed on both sides of the dummy gate; forming a source or a drain on the plurality of strip fins; depositing an interlayer dielectric layer, and performing chemical mechanical planarization (CMP) on the interlayer dielectric layer to expose the top surfaces of the dummy gates; forming a single diffusion break in a single diffusion region; and replacing the dummy gates other than the dummy gate in the single diffusion region with metal gates.