FinFET Fabrication via Solid-State Doping for Leakage Prevention
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Solution Overview
Problem
Current FinFET fabrication methods face challenges with current leakage due to design bottlenecks in the fin-shaped structure, affecting the overall performance of the device.
Innovation Solution
A method involving solid-state doping (SSD) is employed, where a doped layer is formed on the bottom portion of fin-shaped structures, and an annealing process drives dopants into the substrate to create an anti-punch-through (APT) layer, preventing current leakage. The process includes forming spacers as masks to shape the fin structures and using specific materials like borosilicate glass (BSG) for NMOS and phosphosilicate glass (PSG) for PMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional FinFET fabrication methods are used, then the device structure is simple and manufacturing is easier, but current leakage occurs due to punch-through effects
Solution Approach 1:
The fin structure is segmented into multiple regions with different doping concentrations. The method forms a first doped layer with a first doping concentration and a second doped layer with a second doping concentration, creating a segmented doping profile that prevents punch-through while maintaining structural control
Solution Approach 2:
Different regions of the fin structure are given different local properties through selective doping. The bottom portion of the fin receives a first doping concentration while other regions receive different doping concentrations, creating local quality variations that prevent current leakage without requiring complete structural redesign
2Reliability
If the fin-shaped structure is optimized to prevent current leakage, then device performance improves, but the fabrication process becomes more complex
Solution Approach 1:
The method performs preliminary doping actions by forming doped layers on the fin structure before final device completion. The first and second doped layers are formed in advance with specific doping concentrations, preparing the structure to prevent punch-through effects in subsequent processing steps
Solution Approach 2:
The patent uses intermediary doped layers as mediators between the fin structure and the final device operation. These doped layers act as intermediate structures that control carrier flow and prevent direct punch-through, simplifying the overall manufacturing by providing a controlled intermediate state
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SSD technique effectively reduces current leakage by forming a doped region with a v-shaped profile, enhancing the control over the channel region and improving the performance of FinFET devices by preventing punch-through issues.
Implementation Method 1
an annealing process drives dopants into the substrate to create an anti-punch-through (APT) layer
Data Source
AI summary
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a first spacer adjacent to the first fin-shaped structure and a second spacer adjacent to the second fin-shaped structure; and using the first spacer and the second spacer as mask to remove part of the substrate for forming a third fin-shaped structure on the first region and a fourth fin-shaped structure on the second region, in which the third fin-shaped structure includes a first top portion and a first bottom portion and the fourth fin-shaped structure includes a second top portion and a second bottom portion.