FinFET Source-Degenerated Transistor Layout for Flicker Noise Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing transistor noise, particularly flicker noise, which affects the performance and integration density of electronic components.
Innovation Solution
The formation of coupled pairs of source-degenerated transistors, where the source degeneration resistors are integrated using the same processing steps as the transistors, allowing for reduced device size and manufacturing cost. These resistors can be passive or variable, with resistance controlled by an applied voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If source degeneration resistors are integrated using the same processing steps as transistors, then device size and manufacturing cost are reduced, but transistor noise (particularly flicker noise) reduction becomes more challenging
Solution Approach 1:
The patent combines the formation of source degeneration resistors with the transistor fabrication process by using the same epitaxial growth and doping steps. The resistors are formed in dedicated regions within the semiconductor fins during the same processing sequence as the transistor structures, eliminating the need for separate resistor fabrication steps and reducing overall device complexity while maintaining noise reduction functionality.
Solution Approach 2:
The patent applies different doping concentrations and epitaxial growth conditions to specific regions of the semiconductor fin to create distinct functional zones. By controlling the local doping profiles in the resistor regions versus the transistor channel regions, the patent achieves both low-noise resistor characteristics and high-performance transistor characteristics from the same material structure.
2Ease of manufacture
If source degeneration resistors are integrated using the same processing steps as transistors, then manufacturing cost is reduced, but additional process steps would be required
Solution Approach 1:
The patent designs the epitaxial growth and doping processes to serve multiple functions simultaneously. The same epitaxial reactor and doping equipment are used to form both transistor channels and source degeneration resistors in different spatial regions of the wafer during identical processing cycles, making the manufacturing process universal and eliminating the need for dedicated resistor fabrication equipment or separate processing lines.
Solution Approach 2:
The patent merges the resistor formation operations into the transistor fabrication workflow by coordinating the timing and spatial distribution of doping and epitaxial growth steps. Regions designated for resistors receive appropriate doping treatments during the same sequence of operations that form transistor channels, effectively combining two manufacturing functions into one integrated process flow.
3Productivity
If integration density is increased by reducing minimum feature size, then more components can be integrated into a given area, but transistor noise increases
Solution Approach 1:
The patent implements spatially varying doping concentrations within the semiconductor fin structure to create regions with optimized noise characteristics. By controlling the local doping profiles in source degeneration regions versus channel regions, the patent achieves noise reduction at the transistor level while maintaining the scaled dimensions required for high integration density.
Solution Approach 2:
The patent uses composite doping strategies within the semiconductor fin, combining differently doped regions to create a multi-functional structure. The same physical fin contains both low-doped channel regions for high mobility and high-doped source degeneration regions for noise reduction, effectively using material composition variation to resolve the noise-density tradeoff.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces transistor noise, improves device performance, and allows for higher integration density without additional process steps, thereby enhancing the efficiency and flexibility of semiconductor devices.
Implementation Method 1
A first doped region of the fin that extends from the first epitaxial source region toward the epitaxial common region is formed by implanting ions
Data Source
AI summary
A device includes a fin on a substrate; a first transistor, including: a drain region and a first source region in the fin; and a first gate structure on the fin between the first source region and the drain region; a second transistor, including: the drain region and a second source region in the fin; and a second gate structure on the fin between the second source region and the drain region; a first resistor, including: the first source region and a first resistor region in the fin; and a third gate structure on the fin between the first source region and the first resistor region; and a second resistor, including: the second source region and a second resistor region in the fin; and a fourth gate structure on the fin between the second source region and the second resistor region.