Source/Drain Contact Depth Control in FinFET Metallization
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Solution Overview
Problem
In the manufacturing of fin field effect transistors (FinFETs), the proximity of source/drain metallization layers to adjacent conductive structures leads to unwanted parasitic capacitance and electrical short circuits, compromising device performance.
Innovation Solution
A method is introduced to control the depth of source/drain contacts by forming a conformal liner within the fin cut opening, which defines a trench over the shallow trench isolation layer, preventing the metallization layer from extending too deeply and thus reducing parasitic capacitance and short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source/drain metallization layers are extended to contact source/drain regions, then electrical connectivity is improved, but parasitic capacitance and electrical short circuits increase due to proximity to adjacent conductive structures
Solution Approach 1:
The patent segments the fin structure by introducing fin cuts that divide continuous fins into separate sections. This segmentation creates isolated contact regions where metallization can be applied without extending into areas adjacent to other conductive structures, thereby maintaining electrical connectivity while reducing parasitic capacitance and short circuit risks.
Solution Approach 2:
The patent extracts or removes portions of the fin structure through fin cuts to create isolation regions. By taking out these specific fin sections, the design prevents metallization layers from contacting adjacent conductive structures, eliminating the harmful parasitic effects while preserving necessary electrical connections in active regions.
2Object-affected harmful factors
If fin cuts are introduced to isolate conductive structures, then parasitic capacitance and short circuits are reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent merges the fin cut process with existing self-aligned fabrication steps. By integrating fin cuts into the established self-aligned process flow, the additional isolation steps are combined with routine manufacturing operations, minimizing the increase in overall device complexity and manufacturing burden.
Solution Approach 2:
The fin cut structure serves multiple functions: it isolates conductive structures to reduce parasitic effects, defines contact regions for metallization, and maintains compatibility with self-aligned processes. This multi-functionality reduces the need for separate dedicated isolation steps, thereby limiting the increase in device complexity.
3Manufacturing precision
If self-aligned process is used to produce thin fins, then manufacturing precision is improved, but device activation requires high thermal budget that may affect functional gate materials
Solution Approach 1:
The patent introduces a sacrificial gate structure before device activation. This preliminary gate structure protects the eventual functional gate materials from the high thermal budget required for activation. The sacrificial gate absorbs the thermal stress during activation, and is later replaced with the functional gate, thereby enabling precise fin formation through self-aligned processes without exposing functional gate materials to damaging temperatures.
Solution Approach 2:
The sacrificial gate acts as an intermediary structure during the fabrication process. It temporarily occupies the gate region during activation, shielding the future functional gate materials from high temperatures. After activation is complete, the sacrificial gate is removed and replaced with the functional gate, thus mediating between the need for high thermal budget activation and the protection of temperature-sensitive functional gate materials.
Data Source
AI summary
A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.