FinFET Source-Drain Structure for Low Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for forming source and drain features in FinFET devices result in defect issues, dislocation variations, and degrade device performance due to contact resistance and strain effects, limiting the ability to form features with respective characteristics.
Innovation Solution
A two-step etching process is employed to form epitaxial grown source and drain features, including a first etching step to recess the source and drain regions and a second etching step to remove dielectric layers on the fin active regions, followed by epitaxial growth to enhance strain effect and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If selective epitaxial growth is used to form source and drain features, then strain effect is enhanced, but dislocation variation and defect issues occur
Solution Approach 1:
The source and drain regions are segmented into multiple epitaxial growth stages with different conditions. The first epitaxial growth forms initial source/drain regions with controlled strain, while the second epitaxial growth fills recessed areas with different material composition. This segmentation allows strain enhancement in controlled zones while preventing dislocation propagation through interface design between the two growth regions.
Solution Approach 2:
Different material compositions and growth conditions are applied to different spatial locations. The epitaxial growth process creates regions with varying germanium content and crystal orientations - higher Ge content in areas requiring strain enhancement, lower Ge content in areas prone to dislocation. This local quality variation optimizes strain effect where needed while maintaining reliability in defect-prone areas.
2Ease of manufacture
If conventional source and drain formation methods are used, then manufacturing simplicity is maintained, but contact resistance increases and device performance degrades
Solution Approach 1:
The method performs preliminary recessing of source/drain regions before final epitaxial growth. This preliminary action creates controlled voids that are subsequently filled with high-quality epitaxial material having optimized electrical properties. By preparing the structure in advance with recesses, the final contact regions achieve lower contact resistance while the overall process remains integrated with standard FinFET manufacturing flows.
Solution Approach 2:
The epitaxial growth process acts as an intermediary between the silicon substrate and the metal contact layers. This intermediate epitaxial layer with tailored composition and structure serves as a transition region that reduces contact resistance between the silicon channel and metal contacts, while maintaining compatibility with existing manufacturing processes.
3Manufacturing precision
If source and drain features are formed with uniform characteristics, then manufacturing consistency is improved, but the ability to tailor features for different FET types (logic and memory) is reduced
Solution Approach 1:
The epitaxial growth process is made dynamic by allowing different growth conditions for different device regions. The method enables independent control of growth rate, temperature, and gas flow for logic device regions versus memory device regions. This dynamic process control allows each FET type to receive optimized source/drain features tailored to its specific performance requirements while maintaining overall manufacturing consistency through automated process sequencing.
Solution Approach 2:
Different material compositions and structural characteristics are applied locally to different FET types. Logic devices receive source/drain regions with one set of epitaxial parameters optimized for high-speed operation, while memory devices receive source/drain regions with different parameters optimized for retention and switching characteristics. This local quality differentiation enables versatile device performance while maintaining a unified manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method increases carrier mobility and enhances device performance by forming source and drain features with reduced contact resistance and tailored characteristics for different types of FETs, such as logic and memory devices.
Implementation Method 1
epitaxial growth to enhance strain effect and reduce contact resistance
Data Source
AI summary
A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.