FinFET Source/Drain Multilayer Structure for Lower DIBL Leakage
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Solution Overview
Problem
The challenge of forming reliable semiconductor structures, particularly FinFETs, arises from the difficulty in fabricating complex and small-scale circuitry due to advancements in IC materials and design, which complicates processing and manufacturing.
Innovation Solution
A method involving a gate-replacement process is employed to form FinFETs, utilizing a multi-layer source/drain structure with epitaxial growth of silicon layers and blocking layers to enhance conductivity and reduce leakage, combined with dielectric spacers to improve the reliability and performance of the semiconductor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes continue to decrease to increase functional density, then the number of interconnected devices per chip area increases, but fabrication processes become more difficult and reliability decreases
Solution Approach 1:
The source/drain structure is divided into multiple epitaxial layers with different compositions and doping types (e.g., SiGe layer, Si layer, doped regions). This segmentation allows each layer to be optimized for specific functions such as stress management, carrier mobility enhancement, and electrical conductivity, thereby maintaining reliability while enabling smaller feature sizes
Solution Approach 2:
Different regions of the source/drain structure are assigned different material compositions and doping concentrations. For example, SiGe is used in specific regions to induce compressive or tensile stress locally, while heavily doped regions provide low resistance contacts. This local optimization enables continued scaling while maintaining device performance and fabrication reliability
2Reliability
If multi-layer source/drain structure is formed to improve conductivity, then on-resistance decreases, but device complexity increases
Solution Approach 1:
Multiple functions are merged into the source/drain structure by integrating stress-induced layers, doping regions, and contact structures into a unified multi-layer epitaxial system. This combining approach achieves improved conductivity and stress management without requiring separate processing steps for each function, thereby limiting the increase in overall device complexity
Solution Approach 2:
The source/drain structure employs composite materials including SiGe, Si, and various doped regions with different crystal orientations. These composite materials provide synergistic effects where SiGe induces stress to enhance carrier mobility, while doped regions provide electrical conductivity, achieving improved on-resistance through material composition rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the electrical conductivity and reduces drain-induced barrier lowering (DIBL) effects, improving the on-resistance (Ron) of FinFETs while maintaining structural integrity and reliability.
Implementation Method 1
The atomic radius of the first N-type dopant is greater than the atomic radius the second N-type dopant. The first N-type dopant may suppress the second N-type dopant from diffusing into a channel region of the FinFET.
Implementation Method 2
A method involving a gate-replacement process is employed to form FinFETs, utilizing a multi-layer source/drain structure with epitaxial growth of silicon layers
Data Source
AI summary
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure formed over first and second fin structures, and a gate spacer layer formed on a sidewall surface of the gate structure. The semiconductor structure includes a first source/drain (S/D) epitaxial structure formed adjacent to the gate structure in the first fin structure. The S/D epitaxial structure comprises first and second S/D epitaxial layers. The semiconductor structure may include a second S/D epitaxial structure formed adjacent to the gate structure in the second fin structure. A contact structure may be formed over the first and second S/D epitaxial structures.